{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,25]],"date-time":"2026-10-25T05:07:28Z","timestamp":1792904848749,"version":"4.5.0"},"reference-count":73,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2016,10,1]],"date-time":"2016-10-01T00:00:00Z","timestamp":1475280000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2016,10]]},"DOI":"10.1109\/tcad.2015.2513673","type":"journal-article","created":{"date-parts":[[2015,12,30]],"date-time":"2015-12-30T14:07:04Z","timestamp":1451484424000},"page":"1591-1604","source":"Crossref","is-referenced-by-count":484,"title":["A Survey and Evaluation of FPGA High-Level Synthesis Tools"],"prefix":"10.1109","volume":"35","author":[{"given":"Razvan","family":"Nane","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Vlad-Mihai","family":"Sima","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Christian","family":"Pilato","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jongsok","family":"Choi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Blair","family":"Fort","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Andrew","family":"Canis","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yu Ting","family":"Chen","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hsuan","family":"Hsiao","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Stephen","family":"Brown","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Fabrizio","family":"Ferrandi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jason","family":"Anderson","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Koen","family":"Bertels","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref73","doi-asserted-by":"publisher","DOI":"10.2197\/ipsjjip.17.242"},{"key":"ref72","year":"2015","journal-title":"Virtex-5 FPGA data sheet"},{"key":"ref71","year":"2015","journal-title":"Stratix GX FPGA Data Sheet"},{"key":"ref70","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2012.6416721"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1007\/BFb0097941"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344720"},{"key":"ref33","year":"2016","journal-title":"Synphony C Compiler"},{"key":"ref32","year":"2016","journal-title":"C2H Compiler—Discontinued"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-46117-5_90"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2007.107"},{"key":"ref37","year":"2016","journal-title":"AccelDSP Synthesis Tool"},{"key":"ref36","year":"2016","journal-title":"MATCH Compiler"},{"key":"ref35","year":"2016","journal-title":"BDTI High-Level Synthesis Tool Certification Program"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2002.1033026"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554775"},{"key":"ref62","first-page":"171","article-title":"conditional speculation and its effects on performance and area for high-level synthesis","author":"gupta","year":"2001","journal-title":"International Symposium on System Synthesis (IEEE Cat No 01EX526) ISSS-01"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1145\/277044.277067"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2006.1594800"},{"key":"ref28","year":"2016","journal-title":"Altium Designer A Unified Solution"},{"key":"ref64","first-page":"780","article-title":"A gradual scheduling framework for problem size reduction and cross basic block parallelism exploitation in high-level synthesis","author":"zheng","year":"2013","journal-title":"Proc IEEE\/ACM ASP-DAC"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2003.1183177"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2013.6718365"},{"key":"ref66","first-page":"5","article-title":"Harnessing the power of FPGAs using Altera’s OpenCL compiler","author":"singh","year":"2013","journal-title":"Proc ACM FPGA"},{"key":"ref29","year":"2016","journal-title":"GAUT High-Level Synthesis Tool from C to RTL"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1145\/192724.192755"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1109\/HICSS.1993.283949"},{"key":"ref2","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4020-8588-8","author":"coussy","year":"2008","journal-title":"High-Level Synthesis from Algorithm to Digital Circuit"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2008.4484885"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1941487.1941507"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1220583"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1998.707890"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/2.839323"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2010.28"},{"key":"ref23","author":"explorations","year":"2016","journal-title":"EXCite C to RTL Behavioral Synthesis 4 1(a)"},{"key":"ref26","year":"2016","journal-title":"C-to-Silicon Compiler"},{"key":"ref25","year":"2016","journal-title":"Catapult Product Family Overview"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-11970-5_16"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554780"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.41"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1145\/988952.988992"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176646"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2011.44"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645543"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2011.2177706"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554771"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/CODES-ISSS.2013.6659002"},{"key":"ref10","year":"2016","journal-title":"COSY"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2039370.2039381"},{"key":"ref40","year":"2016","journal-title":"MaxCompiler"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2004.1281665"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/43.898829"},{"key":"ref14","year":"2016","journal-title":"AutoESL High-Level Synthesis Tool"},{"key":"ref15","first-page":"69","article-title":"Bluespec system verilog: Efficient, correct RTL from high level specifications","author":"nikhil","year":"2004","journal-title":"Proc of IEEE\/ACM MEMOCODE"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/2.839324"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2012.29"},{"key":"ref18","year":"2016","journal-title":"Impulse CoDeveloper C-to-FPGA Tools"},{"key":"ref19","year":"2016","journal-title":"DK Design Suite Handel-C to FPGA for Algorithm Design"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2014.6853195"},{"key":"ref3","first-page":"641","article-title":"Compositional system-level design exploration with planning of high-level synthesis","author":"liu","year":"2012","journal-title":"Proc IEEE\/ACM DATE"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/s10617-012-9096-8"},{"key":"ref5","first-page":"161","article-title":"Optimizing FPGA-based accelerator design for deep convolutional neural networks","author":"zhang","year":"2015","journal-title":"Proc ACM FPGA"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645550"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339221"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.1996.554030"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950423"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1016\/0167-9260(94)90011-6"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.4218\/etrij.11.0110.0654"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1145\/192724.192731"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/2656075.2656098"},{"key":"ref42","year":"2016","journal-title":"Cynthesizer Solution"},{"key":"ref41","first-page":"3","article-title":"Kiwi: Synthesis of FPGA circuits from parallel programs","author":"greaves","year":"2008","journal-title":"Proc IEEE FCCM"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2110592"},{"key":"ref43","year":"2016","journal-title":"Vivado Design Suite—VivadoHLS"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/7563474\/07368920.pdf?arnumber=7368920","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:46:01Z","timestamp":1641987961000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7368920\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10]]},"references-count":73,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2015.2513673","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,10]]}}}