{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,14]],"date-time":"2026-07-14T12:07:32Z","timestamp":1784030852811,"version":"3.55.0"},"reference-count":20,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2016,10,1]],"date-time":"2016-10-01T00:00:00Z","timestamp":1475280000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/100005144","name":"Qualcomm Research","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100005144","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2016,10]]},"DOI":"10.1109\/tcad.2016.2523983","type":"journal-article","created":{"date-parts":[[2016,2,3]],"date-time":"2016-02-03T14:11:25Z","timestamp":1454508685000},"page":"1707-1720","source":"Crossref","is-referenced-by-count":26,"title":["Adaptive Regression-Based Thermal Modeling and Optimization for Monolithic 3-D ICs"],"prefix":"10.1109","volume":"35","author":[{"given":"Sandeep Kumar","family":"Samal","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shreepad","family":"Panth","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kambiz","family":"Samadi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mehdi","family":"Saeidi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yang","family":"Du","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sung Kyu","family":"Lim","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2273986"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2014.6831837"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6479040"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744917"},{"key":"ref14","year":"2013","journal-title":"OpenSPARC T2"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2010.5419887"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2285593"},{"key":"ref17","year":"2013","journal-title":"Salford Systems"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2012.293"},{"key":"ref19","article-title":"Thermal analysis and model identification techniques for a logic + WIDEIO stacked DRAM test chip","author":"beneventi","year":"2014","journal-title":"Proc Design Autom Test Eur Conf Exhibition (DATE)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993673"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835959"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996800"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382591"},{"key":"ref8","first-page":"1","article-title":"Statistical thermal evaluation and mitigation techniques for 3D chip-multiprocessors in the presence of process variations","author":"juan","year":"2011","journal-title":"Proc DATE"},{"key":"ref7","first-page":"590","article-title":"3D-STAF: Scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits","author":"zhou","year":"2007","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796518"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2012.2223593"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.77"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/343647.343713"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/7563474\/07398000.pdf?arnumber=7398000","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:43:28Z","timestamp":1641987808000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7398000\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10]]},"references-count":20,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2016.2523983","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,10]]}}}