{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,2]],"date-time":"2026-06-02T13:19:59Z","timestamp":1780406399341,"version":"3.54.1"},"reference-count":38,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2016,1,1]],"date-time":"2016-01-01T00:00:00Z","timestamp":1451606400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"The Natural Sciences and Engineering Research Council of Canada NSERC"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2016]]},"DOI":"10.1109\/tcad.2016.2538087","type":"journal-article","created":{"date-parts":[[2016,3,3]],"date-time":"2016-03-03T19:13:40Z","timestamp":1457032420000},"page":"2118-2130","source":"Crossref","is-referenced-by-count":16,"title":["Automated Selection of Assertions for Bit-Flip Detection During Post-Silicon Validation"],"prefix":"10.1109","volume":"35","author":[{"given":"Pouya","family":"Taatizadeh","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Nicola","family":"Nicolici","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2015.7357083"},{"key":"ref33","first-page":"201","article-title":"Formal methods for analyzing the completeness of an assertion suite against a high-level fault model","author":"das","year":"2005","journal-title":"Proc Int Conf VLSI Design"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/FMCAD.2008.ECP.29"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.0342"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2010.5419813"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2011.5722197"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2014.2380272"},{"key":"ref35","first-page":"1","article-title":"Mining-guided state justification with partitioned navigation tracks","author":"parikh","year":"2007","journal-title":"Proc IEEE Int Test Conf (ITC)"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2002.1033793"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2012.6164951"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"373","DOI":"10.1145\/1391469.1391569","article-title":"ifra: instruction footprint recording and analysis for post-silicon bug localization in processors","author":"sung-boem park","year":"2008","journal-title":"2008 45th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2002.1003792"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2010.5699215"},{"key":"ref14","author":"foster","year":"2004","journal-title":"Assertion-Based Design"},{"key":"ref15","first-page":"58","article-title":"Practical assertion-based formal verification for SoC designs","author":"yeung","year":"2005","journal-title":"Proc Int Symp Syst -on-Chip"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2008.0110"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.38"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/10722167_40"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4020-8586-4"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065786"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2002.1003792"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/HASE.2005.6"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20050194"},{"key":"ref6","year":"2003","journal-title":"Intel Platform and Component Validation"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2241176"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146916"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2009.53"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837280"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024856"},{"key":"ref9","first-page":"91","article-title":"Automating post-silicon debugging and repair","author":"chang","year":"2007","journal-title":"Proc ACM\/IEEE Comput Aided Design"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837279"},{"key":"ref20","first-page":"90","article-title":"A case study of time-multiplexed assertion checking for post-silicon debugging","author":"gao","year":"2010","journal-title":"Proc IEEE Int High Level Design Validation Test Workshop (HLDVT)"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1989.100747"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/12.54853"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2008.4484858"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105391"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2005.30"},{"key":"ref25","first-page":"982","article-title":"Automated data analysis solutions to silicon debug","author":"yang","year":"2009","journal-title":"Proc Conf Design Autom Test Europe Conf Exhibit (DATE)"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/7748585\/07425175.pdf?arnumber=7425175","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:19:27Z","timestamp":1642004367000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7425175\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"references-count":38,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2016.2538087","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016]]}}}