{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,21]],"date-time":"2026-01-21T04:38:54Z","timestamp":1768970334565,"version":"3.49.0"},"reference-count":23,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2016,1,1]],"date-time":"2016-01-01T00:00:00Z","timestamp":1451606400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100001348","name":"Research Grant for the Human-Centered Cyber-Physical Systems Programme at the Advanced Digital Sciences Center from Singapore\u2019s Agency for Science, Technology and Research","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001348","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2016]]},"DOI":"10.1109\/tcad.2016.2552821","type":"journal-article","created":{"date-parts":[[2016,4,11]],"date-time":"2016-04-11T18:07:18Z","timestamp":1460398038000},"page":"2032-2045","source":"Crossref","is-referenced-by-count":5,"title":["FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow"],"prefix":"10.1109","volume":"35","author":[{"given":"Ying","family":"Chen","sequence":"first","affiliation":[]},{"given":"Tan","family":"Nguyen","sequence":"additional","affiliation":[]},{"given":"Yao","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Swathi T.","family":"Gurumani","sequence":"additional","affiliation":[]},{"given":"Yun","family":"Liang","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2908-2225","authenticated-orcid":false,"given":"Kyle","family":"Rupnow","sequence":"additional","affiliation":[]},{"given":"Jason","family":"Cong","sequence":"additional","affiliation":[]},{"given":"Wen-Mei","family":"Hwu","sequence":"additional","affiliation":[]},{"given":"Deming","family":"Chen","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2497259"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2012.6412118"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-89740-8_2"},{"key":"ref13","year":"2015","journal-title":"Vivado High-Level Synthesis"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2514641.2514652"},{"key":"ref15","year":"2015","journal-title":"Vivado High-Level Synthesis"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847344"},{"key":"ref17","year":"2012","journal-title":"7 Series FPGAs Configurable Logic Block"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372592"},{"key":"ref19","year":"2015","journal-title":"AR# 62720 Vivado Implementation—Placer Reports Higher LUTs Utilization in ‘ERROR [Place 30-380]’ Than What Is Seen in the Post-Opt Utilization Report"},{"key":"ref4","year":"2015","journal-title":"Opencl 1 2 reference pages"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1365490.1365500"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/SASP.2009.5226333"},{"key":"ref5","year":"2012","journal-title":"CUDA C Programming Guide"},{"key":"ref8","author":"pasricha","year":"2010","journal-title":"On-Chip Communication Architectures System on Chip Interconnect"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2011.29"},{"key":"ref2","first-page":"202","article-title":"The free lunch is over: A fundamental turn toward concurrency in software","volume":"30","author":"sutter","year":"2005","journal-title":"Dr Dobb’s J"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2005.160"},{"key":"ref9","article-title":"An analytical model of logic resource utilization for FPGA architecture development","author":"lam","year":"2010"},{"key":"ref20","year":"2015","journal-title":"CUDA Zone"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554771"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105399"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/7748585\/07450674.pdf?arnumber=7450674","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:19:28Z","timestamp":1642004368000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7450674\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"references-count":23,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2016.2552821","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016]]}}}