{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:00:17Z","timestamp":1740132017811,"version":"3.37.3"},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100003711","name":"Ministry of Science and Technology of Taiwan, China","doi-asserted-by":"publisher","award":["100-2221-E-007-126-MY3","102-2221-E-033-064-MY3"],"award-info":[{"award-number":["100-2221-E-007-126-MY3","102-2221-E-033-064-MY3"]}],"id":[{"id":"10.13039\/501100003711","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2017,1]]},"DOI":"10.1109\/tcad.2016.2565202","type":"journal-article","created":{"date-parts":[[2016,5,9]],"date-time":"2016-05-09T18:25:02Z","timestamp":1462818302000},"page":"146-155","source":"Crossref","is-referenced-by-count":2,"title":["Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction"],"prefix":"10.1109","volume":"36","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9792-5370","authenticated-orcid":false,"given":"Chung-Han","family":"Chou","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yen-Ting","family":"Lai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yi-Chun","family":"Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chih-Yu","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Liang-Chia","family":"Cheng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shih-Hsu","family":"Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shih-Chieh","family":"Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/383082.383124"},{"key":"ref30","doi-asserted-by":"crossref","first-page":"1593","DOI":"10.1109\/TVLSI.2008.2006477","article-title":"Implementing multiphase resonant clocking on a finite-impulse response filter","volume":"17","author":"yu","year":"2009","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2190671"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2066650"},{"key":"ref12","first-page":"263","article-title":"A multiple level network approach for clock skew minimization with process variations","author":"mori","year":"2004","journal-title":"Proc Asia South Pacific Design Autom Conf"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065629"},{"journal-title":"ASITIC Analysis of Si inductors and transformers for ICs","year":"2015","author":"niknejad","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2160916.2160950"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/775832.776005"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2061130"},{"key":"ref18","first-page":"144","article-title":"The clock distribution of the POWER4 microprocessor","author":"restle","year":"2002","journal-title":"Proc ISSCC"},{"key":"ref19","first-page":"558","article-title":"Clock buffer polarity assignment for power noise reduction","author":"samanta","year":"2006","journal-title":"Proc IEEE Int Conf Comput -Aided Design"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5653732"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.880610"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/4.962285"},{"key":"ref3","first-page":"342","article-title":"A 4.6 GHz resonant global clock distribution network","author":"chan","year":"2004","journal-title":"Proc ISSCC"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/12.280806"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.33"},{"key":"ref5","first-page":"376","article-title":"Skew aware polarity assignment in clock tree","author":"chen","year":"2007","journal-title":"Proc IEEE Int Conf Comput Aided Design"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.831435"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1996.545607"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007147"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837295"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2003.1240902"},{"key":"ref20","first-page":"68","article-title":"Resonant clock design for a power-efficient high-volume x86-64 microprocessor","author":"sathe","year":"2012","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2338862"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/1529255.1529266"},{"article-title":"Implementing differential resonant clock with DC blocking capacitor","year":"2014","author":"van goor","key":"ref24"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2637481"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1996.569827"},{"key":"ref25","first-page":"563","article-title":"Combinatorial algorithms for fast clock mesh optimization","author":"venkataraman","year":"2006","journal-title":"Proc Int Conf Comput -Aided Design"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/7790916\/07466841.pdf?arnumber=7466841","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:20:15Z","timestamp":1642004415000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7466841\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,1]]},"references-count":31,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2016.2565202","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2017,1]]}}}