{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,25]],"date-time":"2025-10-25T18:44:37Z","timestamp":1761417877055},"reference-count":23,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2016,1,1]],"date-time":"2016-01-01T00:00:00Z","timestamp":1451606400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2016]]},"DOI":"10.1109\/tcad.2016.2587278","type":"journal-article","created":{"date-parts":[[2016,7,1]],"date-time":"2016-07-01T18:14:27Z","timestamp":1467396867000},"page":"1-1","source":"Crossref","is-referenced-by-count":6,"title":["A Unified Design Flow to Automatically Generate On-Chip Monitors during High-Level Synthesis of Hardware Accelerators"],"prefix":"10.1109","author":[{"given":"Mohamed","family":"Hammouda","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Philippe","family":"Coussy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Loic","family":"Lagadec","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"1","article-title":"Assertion support in high-level synthesis design flow","author":"ribon","year":"2011","journal-title":"Forum Specification and Design Languages (FDL)"},{"key":"ref11","year":"2004","journal-title":"Property specification language Reference manual"},{"key":"ref12","year":"2001","journal-title":"SystemVerilog 3 1a Language Reference Manual"},{"key":"ref13","year":"2009","journal-title":"Open Verification Library Reference Manual"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/978-94-007-1125-9_8"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2006.319966"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/262004.262005"},{"key":"ref17","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4020-8588-8","author":"coussy","year":"2008","journal-title":"High-Level Synthesis from Algorithm to Digital Circuit"},{"key":"ref18","article-title":"MoCFI: A framework to mitigate control-flow attacks on smartphones","author":"davi","year":"2012","journal-title":"Proc Network and Distributed System Security Symp (NDSS)"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2591513.2591521"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1991.146682"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/OLT.2003.1214381"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2012.2218630"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.266"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2008.147"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ASICON.2009.5351246"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/24.994926"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2011.101"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2010.5470747"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865091"},{"key":"ref22","first-page":"7","article-title":"Design and verification of digital systems","author":"bertacco","year":"2006","journal-title":"Scalable Hardware Verification with Symbolic Simulation"},{"key":"ref21","year":"2008","journal-title":"Codevelope's Users Guide"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457129"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/6917053\/07503118.pdf?arnumber=7503118","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,2]],"date-time":"2022-07-02T14:59:49Z","timestamp":1656773989000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7503118\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/tcad.2016.2587278","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016]]}}}