{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,23]],"date-time":"2026-04-23T14:45:26Z","timestamp":1776955526083,"version":"3.51.4"},"reference-count":26,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2016,1,1]],"date-time":"2016-01-01T00:00:00Z","timestamp":1451606400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2016]]},"DOI":"10.1109\/tcad.2016.2587687","type":"journal-article","created":{"date-parts":[[2016,7,7]],"date-time":"2016-07-07T20:15:39Z","timestamp":1467922539000},"page":"1-1","source":"Crossref","is-referenced-by-count":5,"title":["LFSR-Based Generation of Multicycle Tests"],"prefix":"10.1109","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5491-7282","authenticated-orcid":false,"given":"Irith","family":"Pomeranz","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2193583"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"90","DOI":"10.1049\/iet-cdt.2013.0101","article-title":"Multi-cycle broadside tests with runs of constant primary input vectors","volume":"8","author":"pomeranz","year":"2014","journal-title":"IET Comput Digit Tech"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2408257"},{"key":"ref13","first-page":"237","article-title":"LFSR-coded test patterns for scan designs","author":"koenemann","year":"1991","journal-title":"Proc Eur Test Conf"},{"key":"ref14","first-page":"120","article-title":"Generation of vector patterns through reseeding of multiple-polynomial linear feedback shift register","author":"hellebrand","year":"1992","journal-title":"Proc Int Test Conf"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966696"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041773"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2007.4437611"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2126574"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2011.70"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966682"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1996.556969"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2007.4437648"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/775832.776000"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2010.5469580"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700648"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.1998.741614"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2138470"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"1128","DOI":"10.1109\/43.406714","article-title":"Test application time reduction for sequential circuits with scan","volume":"14","author":"lee","year":"1995","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2012.6378229"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/LATW.2015.7102512"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2012.41"},{"key":"ref24","first-page":"2392","article-title":"Computing seeds for LFSR-based test generation from nontest cubes","volume":"24","author":"pomeranz","year":"2016","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2459031"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1230800.1230810"},{"key":"ref25","author":"bardell","year":"1987","journal-title":"Built-In Test for VLSI Pseudorandom Techniques"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/6917053\/07505979.pdf?arnumber=7505979","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,6,18]],"date-time":"2024-06-18T04:26:05Z","timestamp":1718684765000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7505979\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"references-count":26,"URL":"https:\/\/doi.org\/10.1109\/tcad.2016.2587687","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016]]}}}