{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,6]],"date-time":"2026-03-06T13:19:17Z","timestamp":1772803157602,"version":"3.50.1"},"reference-count":34,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2017,8,1]],"date-time":"2017-08-01T00:00:00Z","timestamp":1501545600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["2470"],"award-info":[{"award-number":["2470"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2017,8]]},"DOI":"10.1109\/tcad.2016.2629422","type":"journal-article","created":{"date-parts":[[2016,11,16]],"date-time":"2016-11-16T16:39:47Z","timestamp":1479314387000},"page":"1406-1419","source":"Crossref","is-referenced-by-count":8,"title":["Prebond Testing and Test-Path Design for the Silicon Interposer in 2.5-D ICs"],"prefix":"10.1109","volume":"36","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1434-5662","authenticated-orcid":false,"given":"Ran","family":"Wang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zipeng","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sukeshwar","family":"Kannan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4475-6435","authenticated-orcid":false,"given":"Krishnendu","family":"Chakrabarty","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","author":"jones","year":"2010","journal-title":"Technical Viability of Stacked Silicon Interconnect Technology"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2011.5898527"},{"key":"ref31","first-page":"847","article-title":"Silicon interposer with TSVs (through silicon vias) and fine multilayer wiring","author":"sunohara","year":"2008","journal-title":"Proc IEEE Electron Compon Technol Conf"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2012.07.021"},{"key":"ref34","author":"dorsey","year":"2010","journal-title":"Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity Bandwidth and Power Efficiency"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2013.6651906"},{"key":"ref11","first-page":"67","article-title":"At-speed BIST for interposer wires supporting on-the-spot diagnosis","author":"huang","year":"2013","journal-title":"Proc Int On-Line Testing Symp"},{"key":"ref12","article-title":"Silicon interposer testing for three dimensional chip stack","author":"christo","year":"2011"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2014.15"},{"key":"ref14","article-title":"Interposer testing using dummy connections","author":"lu","year":"2014"},{"key":"ref15","article-title":"3D-IC interposer testing structure and method of testing the structure","author":"tseng","year":"2014"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593111"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2002.802657"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2007.901606"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2002.802657"},{"key":"ref28","volume":"2","author":"west","year":"2001","journal-title":"Introduction to Graph Theory"},{"key":"ref4","first-page":"1","author":"dorsey","year":"2010","journal-title":"Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity Bandwidth and Power Efficiency"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2259626"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2011.6139181"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2013.6651893"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1016\/0304-3975(76)90059-1"},{"key":"ref5","article-title":"Xilinx&#x2019;s 3D (or 2.5 D) packaging enables the world&#x2019;s highest capacity FPGA device, and one of the most powerful processors on the market","author":"yannou","year":"2011","journal-title":"3D Packaging Magazine"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2014.7035334"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.3850\/9783981537079_0740"},{"key":"ref2","article-title":"A silicon interposerbased 2.5 DIC design flow, going 3D by evolution rather than by revolution","author":"jackson","year":"2012","journal-title":"Synopsys Insight Newsletter"},{"key":"ref9","first-page":"1","article-title":"3D-IC interconnect test, diagnosis, and repair","author":"chi","year":"2013","journal-title":"Proc IEEE VLSI Test Symp"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.136"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2006.1705255"},{"key":"ref22","article-title":"Two-step interconnect testing of semiconductor dies","author":"ryckaert","year":"2014"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2007.4418858"},{"key":"ref24","article-title":"Fine pitch probes for semiconductor testing, and a method to fabricate and assemble same","author":"cros","year":"2015"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2008.4550030"},{"key":"ref26","first-page":"52","article-title":"Interconnect testing with boundary scan","author":"wagner","year":"1987","journal-title":"Proc IEEE Int Test Conf"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2015.7112735"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/7982827\/07745927.pdf?arnumber=7745927","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:41:35Z","timestamp":1641987695000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7745927\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,8]]},"references-count":34,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2016.2629422","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,8]]}}}