{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,29]],"date-time":"2026-05-29T13:54:24Z","timestamp":1780062864884,"version":"3.54.0"},"reference-count":59,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2017,11,1]],"date-time":"2017-11-01T00:00:00Z","timestamp":1509494400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100000781","name":"European Research Council","doi-asserted-by":"publisher","award":["H2020-ERC-2014-ADG 669354 CyberCare"],"award-info":[{"award-number":["H2020-ERC-2014-ADG 669354 CyberCare"]}],"id":[{"id":"10.13039\/501100000781","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001711","name":"Swiss National Science Foundation","doi-asserted-by":"publisher","award":["200021-169084 MAJesty"],"award-info":[{"award-number":["200021-169084 MAJesty"]}],"id":[{"id":"10.13039\/501100001711","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2017,11]]},"DOI":"10.1109\/tcad.2017.2664059","type":"journal-article","created":{"date-parts":[[2017,2,7]],"date-time":"2017-02-07T20:55:14Z","timestamp":1486500914000},"page":"1842-1855","source":"Crossref","is-referenced-by-count":72,"title":["Exact Synthesis of Majority-Inverter Graphs and Its Applications"],"prefix":"10.1109","volume":"36","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0229-8766","authenticated-orcid":false,"given":"Mathias","family":"Soeken","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Luca Gaetano","family":"Amaru","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Pierre-Emmanuel","family":"Gaillardon","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Giovanni","family":"De Micheli","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","author":"muroga","year":"1979","journal-title":"Logic Design and Switching Theory"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2007.4397290"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/12.73590"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.2016.21"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2506566"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1979.1675229"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275118"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882484"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/43.644605"},{"key":"ref34","article-title":"FRAIGs: A unifying representation for logic synthesis and verification","author":"mishchenko","year":"2005"},{"key":"ref28","article-title":"Practical SAT—A tutorial on applied satisfiability solving","author":"\u00e9en","year":"2007","journal-title":"Proc FMCAD"},{"key":"ref27","first-page":"32","article-title":"Finding efficient circuits using SAT-solvers","author":"kojevnikov","year":"2009","journal-title":"Proc 12th Int Conf SAT"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1969.222593"},{"key":"ref2","first-page":"365","article-title":"On the (non) NP-hardness of computing circuit complexity","author":"murray","year":"2015","journal-title":"Proc 30th Conf Comput Complexity"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/335305.335314"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/321229.321232"},{"key":"ref22","article-title":"Exact circuit synthesis","author":"drechsler","year":"1998","journal-title":"Proc Int Workshop Logic Synth"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1965.264064"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1287\/opre.19.4.1090"},{"key":"ref23","author":"knuth","year":"2011","journal-title":"The Art of Computer Programming Volume 4A"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1976.1674714"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1972.5008920"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/LMAG.2012.2188621"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1016\/j.spmi.2005.07.001"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1996.563527"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2013.6718374"},{"key":"ref57","first-page":"337","article-title":"Z3: An efficient SMT solver","author":"de moura","year":"2008","journal-title":"Proc TACAS\/ETAPS"},{"key":"ref56","first-page":"15","article-title":"Inversion optimization in majority-inverter graphs","author":"testa","year":"2016","journal-title":"Proc IEEE\/ACM Int Symp Nanoscale Archit (NANOARCH)"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/JXCDC.2015.2418033"},{"key":"ref54","first-page":"1307","article-title":"Logic optimization for majority gate-based nanoelectronic circuits","author":"huo","year":"2006","journal-title":"Proc IEEE Int Symp Circuits Syst (ISCAS)"},{"key":"ref53","doi-asserted-by":"crossref","first-page":"1466","DOI":"10.1126\/science.287.5457.1466","article-title":"Room temperature magnetic quantum cellular automata","volume":"287","author":"cowburn","year":"2000","journal-title":"Science"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1166\/jno.2008.003"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/FOCS.1962.16"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TEC.1962.5219329"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/264995.264996"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.888267"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2009.2028609"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TEC.1960.5219856"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2004.834177"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-27813-9_14"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/FOCS.1961.1"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1147\/rd.62.0227"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1968.227399"},{"key":"ref4","article-title":"Optimal combinational multi-level logic synthesis","author":"ernst","year":"2009"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1006\/jcss.1997.1494"},{"key":"ref6","author":"knuth","year":"2015","journal-title":"The Art of Computer Programming Volume 4 Fascicle 6 Satisfiability"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1972.5009010"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.804386"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593158"},{"key":"ref49","article-title":"A novel basis for logic optimization","author":"haaswijk","year":"2017","journal-title":"Proc Asia South Pacific Des Autom Conf (ASP-DAC)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1963.263531"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-40970-2_12"},{"key":"ref45","first-page":"24","article-title":"ABC: An academic industrial-strength verification tool","author":"brayton","year":"2010","journal-title":"Proc 22nd Int Conf CAV"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/43.273754"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.3850\/9783981537079_0281"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4899-5327-8_25"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1007\/11814948_18"},{"key":"ref44","first-page":"120","article-title":"A method of circuit sythesis","volume":"1","author":"lupanov","year":"1958","journal-title":"Isv Vuzov Radiofizika"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-72788-0_26"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/8071066\/07842552.pdf?arnumber=7842552","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T17:03:00Z","timestamp":1642006980000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7842552\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,11]]},"references-count":59,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2017.2664059","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,11]]}}}