{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:00:28Z","timestamp":1740132028468,"version":"3.37.3"},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2017,12,1]],"date-time":"2017-12-01T00:00:00Z","timestamp":1512086400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100003725","name":"Basic Science Research Program and Nano-Material Technology Development Program through the National Research Foundation of Korea by the Ministry of Science, ICT and Future Planning","doi-asserted-by":"publisher","award":["2013R1A1A1005534","2016M3A7B4909668"],"award-info":[{"award-number":["2013R1A1A1005534","2016M3A7B4909668"]}],"id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2017,12]]},"DOI":"10.1109\/tcad.2017.2682645","type":"journal-article","created":{"date-parts":[[2017,3,15]],"date-time":"2017-03-15T21:46:24Z","timestamp":1489614384000},"page":"1978-1988","source":"Crossref","is-referenced-by-count":8,"title":["Efficient Execution of Stream Graphs on Coarse-Grained Reconfigurable Architectures"],"prefix":"10.1109","volume":"36","author":[{"given":"Sangyun","family":"Oh","sequence":"first","affiliation":[]},{"given":"Hongsik","family":"Lee","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1523-2974","authenticated-orcid":false,"given":"Jongeun","family":"Lee","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744884"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/774789.774805"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.321"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2003.1173050"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.173"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/358923.358939"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2656075.2656085"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"507","DOI":"10.1109\/TVLSI.2015.2474129","article-title":"Improving nested loop pipelining on coarse-grained reconfigurable architectures","volume":"24","author":"yin","year":"2016","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2086696.2086711"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105748"},{"journal-title":"OMAP3530\/25 Applications Processor","year":"2008","key":"ref15"},{"article-title":"Cacti 6.0: A tool to understand large caches","year":"2009","author":"muralimanohar","key":"ref16"},{"journal-title":"ARM PL310 Cache Controller Technical Reference Manual","year":"2004","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.49"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2004.1281665"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372624"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2012.6412149"},{"key":"ref27","first-page":"1","article-title":"Branch-aware loop mapping on CGRAs","author":"hamzeh","year":"2014","journal-title":"Proc 51st Annu Design Autom Conf (DAC)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2008.07.002"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.320"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2486781"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228600"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45937-5_14"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1987.13876"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454140"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/WWC.2001.990739"},{"key":"ref1","first-page":"166","article-title":"DRESC: A retargetable compiler for coarse-grained reconfigurable architectures","author":"mei","year":"2002","journal-title":"Proc IEEE Int Conf Field Program Technol (FPT)"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1379022.1375596"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/1961295.1950409"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2854038.2854055"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/1450095.1450105"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629987"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488756"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2011.6132678"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/8114692\/07879212.pdf?arnumber=7879212","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:39:13Z","timestamp":1641987553000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7879212\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,12]]},"references-count":35,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2017.2682645","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2017,12]]}}}