{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,10]],"date-time":"2026-09-10T23:17:20Z","timestamp":1789082240986,"version":"build-2803163510"},"reference-count":21,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T00:00:00Z","timestamp":1514764800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100003725","name":"Basic Science Research Program through the National Research Foundation of Korea by the Ministry of Education","doi-asserted-by":"publisher","award":["NRF-2015R1D1A1A01058856"],"award-info":[{"award-number":["NRF-2015R1D1A1A01058856"]}],"id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003661","name":"Korea Institute for Advancement of Technology Grant through the Korean Government (Motie:Ministry of Trade, Industry & Energy, HRD Program for Software-SoC Convergence)","doi-asserted-by":"publisher","award":["N0001883"],"award-info":[{"award-number":["N0001883"]}],"id":[{"id":"10.13039\/501100003661","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Ministry of Trade, Industry and Energy through the Korea Semiconductor Research Consortium","award":["10080594"],"award-info":[{"award-number":["10080594"]}]},{"DOI":"10.13039\/100004358","name":"Samsung Research Fund","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100004358","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2018,1]]},"DOI":"10.1109\/tcad.2017.2698025","type":"journal-article","created":{"date-parts":[[2017,4,25]],"date-time":"2017-04-25T18:41:08Z","timestamp":1493145668000},"page":"245-256","source":"Crossref","is-referenced-by-count":13,"title":["Clock Network Optimization With Multibit Flip-Flop Generation Considering Multicorner Multimode Timing Constraint"],"prefix":"10.1109","volume":"37","author":[{"given":"Taehee","family":"Lee","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"David Z.","family":"Pan","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1502-5353","authenticated-orcid":false,"given":"Joon-Sung","family":"Yang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2007.20"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2009.4810370"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2394310"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2002.146755"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378498"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2253338"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2016.7527357"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2106852"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICSICT.2014.7021158"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2894753"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2177460"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2560519.2560520"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2491477.2491484"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2177459"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2165716"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2010.5647784"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2376988"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2451916.2451955"},{"key":"ref9","first-page":"1","article-title":"Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling","author":"echeverri","year":"2014","journal-title":"Proc Conf Design Autom Test Europe"},{"key":"ref20","article-title":"Graph clustering by flow simulation","author":"dongen","year":"2000"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228499"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/8231808\/07911253.pdf?arnumber=7911253","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:24:57Z","timestamp":1642004697000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7911253\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,1]]},"references-count":21,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2017.2698025","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,1]]}}}