{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,23]],"date-time":"2026-07-23T10:14:03Z","timestamp":1784801643694,"version":"3.55.0"},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2017,12,1]],"date-time":"2017-12-01T00:00:00Z","timestamp":1512086400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100004937","name":"German Federal Ministry of Education and Research in the Joint Research Project RESIST","doi-asserted-by":"publisher","award":["16ES0307"],"award-info":[{"award-number":["16ES0307"]}],"id":[{"id":"10.13039\/501100004937","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2017,12]]},"DOI":"10.1109\/tcad.2017.2702615","type":"journal-article","created":{"date-parts":[[2017,5,12]],"date-time":"2017-05-12T17:36:15Z","timestamp":1494610575000},"page":"1954-1967","source":"Crossref","is-referenced-by-count":8,"title":["Analog Power-Down Synthesis"],"prefix":"10.1109","volume":"36","author":[{"given":"Michael","family":"Zwerger","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3216-4969","authenticated-orcid":false,"given":"Maximilian","family":"Neuner","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7626-1958","authenticated-orcid":false,"given":"Helmut","family":"Graeb","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref30","author":"sedgewick","year":"2011","journal-title":"Algorithms"},{"key":"ref10","year":"2011","journal-title":"International Technology Roadmap for Semiconductors"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.0140"},{"key":"ref12","first-page":"41","article-title":"Stress-induced MOSFET mismatch for analog circuits","author":"chen","year":"2001","journal-title":"Proc IEEE Int Integr Rel Workshop Final Rep"},{"key":"ref13","first-page":"81","article-title":"Mismatch drift: A reliability issue for analog MOS circuits","author":"michael","year":"1992","journal-title":"Proc 30th Annu Proc Int Rel Phys Symp"},{"key":"ref14","article-title":"Circuit analyzer systems and methods","author":"georgakos","year":"2014"},{"key":"ref15","year":"2015","journal-title":"Calibre® PERC™ Software"},{"key":"ref16","year":"2015","journal-title":"CustomSim Circuit Check (CCK)"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/978-94-007-0149-6_2"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-013-0107-x"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2006143"},{"key":"ref28","year":"2016","journal-title":"Cadence Design Systems Inc"},{"key":"ref4","author":"scheffer","year":"2006","journal-title":"EDA for IC System Design Verification and Testing"},{"key":"ref27","year":"2016","journal-title":"Silicon Integration Initiative (Si2)"},{"key":"ref3","first-page":"1","article-title":"Power-down schematic synthesis for analog\/mixed-signal circuits","author":"neuner","year":"2016","journal-title":"Proc 15th ITG\/GMM-Fachtagung (Analog)"},{"key":"ref6","author":"lee","year":"2012","journal-title":"Introduction to Low-Power Design in VLSIs"},{"key":"ref29","article-title":"Intersection of two lines in three space","author":"goldman","year":"1993","journal-title":"Graphic Gems"},{"key":"ref5","author":"keating","year":"2007","journal-title":"Low Power Methodology Manual"},{"key":"ref8","first-page":"404","article-title":"Software check for power-down mode of analog circuits","author":"blieck","year":"1996","journal-title":"Proc Eur Solid-State Circuits Conf (ESSCIRC)"},{"key":"ref7","author":"juneja","year":"2015","journal-title":"Power Off or Power Down?"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/SMACD.2016.7520645"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/SMACD.2012.6339384"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372632"},{"key":"ref20","author":"schulte","year":"2015","journal-title":"Modeling and Programming with Gecode"},{"key":"ref22","year":"2016","journal-title":"WiCkeD"},{"key":"ref21","article-title":"Verification and synthesis of analog power-down circuits","author":"zwerger","year":"2017"},{"key":"ref24","year":"2010","journal-title":"Functional Verification of a Differential Operational Amplifier"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/APASIC.2002.1031567"},{"key":"ref26","article-title":"Current bias circuit and current bias start-up circuit thereof","author":"hsiao","year":"2008"},{"key":"ref25","author":"razavi","year":"2000","journal-title":"Design of Analog CMOS Integrated Circuits"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/8114692\/07922518.pdf?arnumber=7922518","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:39:14Z","timestamp":1641987554000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7922518\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,12]]},"references-count":30,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2017.2702615","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,12]]}}}