{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:00:30Z","timestamp":1740132030255,"version":"3.37.3"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2018,2,1]],"date-time":"2018-02-01T00:00:00Z","timestamp":1517443200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"German Research Foundation (DFG)"},{"name":"Transregional Collaborative Research Centre \u201cInvasive Computing\u201d (SFB\/TR 89)"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2018,2]]},"DOI":"10.1109\/tcad.2017.2702632","type":"journal-article","created":{"date-parts":[[2017,5,12]],"date-time":"2017-05-12T21:36:15Z","timestamp":1494624975000},"page":"392-405","source":"Crossref","is-referenced-by-count":17,"title":["Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning"],"prefix":"10.1109","volume":"37","author":[{"given":"Grace Li","family":"Zhang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9752-7201","authenticated-orcid":false,"given":"Bing","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jinglan","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yiyu","family":"Shi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4431-7619","authenticated-orcid":false,"given":"Ulf","family":"Schlichtmann","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Applied Integer Programming Modeling and Solution","year":"2011","author":"chen","key":"ref32"},{"journal-title":"Gurobi Optimizer Reference Manual","year":"2013","key":"ref31"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1214\/aoms\/1177706645"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.917960"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090674"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2012.275"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2432143"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700565"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2009.5355650"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105366"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2209883"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2000248"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/12.55696"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2108030"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859894"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.79"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1493984"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1016\/0041-5553(67)90144-9"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.824706"},{"key":"ref8","first-page":"611","article-title":"A yield improvement methodology using pre- and post-silicon statistical clock scheduling","author":"tsai","year":"2004","journal-title":"Proc Int Conf Comput -Aided Design"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/4.881198"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907047"},{"key":"ref9","first-page":"575","article-title":"Statistical timing analysis driven post-silicon-tunable clock-tree synthesis","author":"tsai","year":"2005","journal-title":"Proc Int Conf Comput -Aided Design"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.3850\/9783981537079_0250"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"8","DOI":"10.1109\/MDT.2003.1232251","article-title":"Delay defect characteristics and testing strategies","volume":"20","author":"kim","year":"2003","journal-title":"IEEE Design Test Comput"},{"journal-title":"Introduction to Algorithms","year":"1990","author":"cormen","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898017"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630004"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996663"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2014.2299279"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691154"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/8263325\/07922504.pdf?arnumber=7922504","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:24:53Z","timestamp":1642004693000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7922504\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,2]]},"references-count":32,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2017.2702632","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2018,2]]}}}