{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:00:29Z","timestamp":1740132029629,"version":"3.37.3"},"reference-count":24,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2017,8,1]],"date-time":"2017-08-01T00:00:00Z","timestamp":1501545600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100004663","name":"Ministry of Science and Technology of Taiwan","doi-asserted-by":"publisher","award":["105-2221-E-002-196-MY3","105-2622-8-002-001","105-2923-E-002-016-MY3"],"award-info":[{"award-number":["105-2221-E-002-196-MY3","105-2622-8-002-001","105-2923-E-002-016-MY3"]}],"id":[{"id":"10.13039\/501100004663","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2017,8]]},"DOI":"10.1109\/tcad.2017.2702649","type":"journal-article","created":{"date-parts":[[2017,5,12]],"date-time":"2017-05-12T21:36:15Z","timestamp":1494624975000},"page":"1251-1264","source":"Crossref","is-referenced-by-count":0,"title":["A Gridless Approach to the Satisfiability of Self-Aligned Triple Patterning"],"prefix":"10.1109","volume":"36","author":[{"given":"Hsiao-Lei","family":"Chien","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mei-Yen","family":"Chiu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2279-4732","authenticated-orcid":false,"given":"Jie-Hong R.","family":"Jiang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1117\/12.879324"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2252054"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024901"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2015.7059085"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2288678"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488818"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2015.7059006"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2387840"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2265309"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1117\/12.896990"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1117\/12.881645"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1117\/12.772953"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1117\/12.918078"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1117\/12.916490"},{"key":"ref8","article-title":"A layout decomposition algorithm for self-aligned multiple patterning","volume":"9053","author":"you","year":"2014","journal-title":"Proc SPIE Design Process Technol Co Optim Manufacturability VIII"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1117\/12.2011261"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2747940"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429430"},{"journal-title":"The Bumpy Road To 10nm FinFETs Semiconductor Engineering","year":"2014","author":"lapedus","key":"ref9"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2717764.2717783"},{"journal-title":"CPLEX Optimizers","year":"2015","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-24605-3_37"},{"key":"ref24","doi-asserted-by":"crossref","first-page":"1","DOI":"10.3233\/SAT190014","article-title":"Translating pseudo-Boolean constraints into SAT","volume":"2","author":"een","year":"2006","journal-title":"J Satisfiability Boolean Model Comput"},{"journal-title":"LP_solve","year":"2015","key":"ref23"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/7982827\/07922519.pdf?arnumber=7922519","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:22:09Z","timestamp":1642004529000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7922519\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,8]]},"references-count":24,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2017.2702649","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2017,8]]}}}