{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,17]],"date-time":"2025-10-17T13:55:26Z","timestamp":1760709326171,"version":"3.37.3"},"reference-count":42,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2017]]},"DOI":"10.1109\/tcad.2017.2705123","type":"journal-article","created":{"date-parts":[[2017,5,18]],"date-time":"2017-05-18T18:40:28Z","timestamp":1495132828000},"page":"1-1","source":"Crossref","is-referenced-by-count":7,"title":["MCXplore: Automating the Validation Process of DRAM Memory Controller Designs"],"prefix":"10.1109","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5926-5861","authenticated-orcid":false,"given":"Mohamed","family":"Hassan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiren","family":"Patel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"2005","journal-title":"Memory Controller Hub (MCH) a Datasheet","key":"ref39"},{"year":"2012","journal-title":"E5-2600 Product Family Uncore Performance Monitoring Guide","key":"ref38"},{"key":"ref33","first-page":"1357","article-title":"MCXplore: An Automated Framework for Validating Memory Controller Designs","author":"mohamed hassan","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"year":"2017","journal-title":"DDR4 Memory Protocol Analysis and Compliance Verification","key":"ref32"},{"year":"2017","journal-title":"VC Verification IP for DRAM Memory","key":"ref31"},{"doi-asserted-by":"publisher","key":"ref30","DOI":"10.1002\/stvr.402"},{"doi-asserted-by":"publisher","key":"ref37","DOI":"10.1109\/MICRO.2007.13"},{"key":"ref36","doi-asserted-by":"crossref","DOI":"10.1007\/3-540-45657-0_29","article-title":"NuSMV 2: An opensource tool for symbolic model checking","author":"cimatti","year":"2002","journal-title":"Computer Aided Verification"},{"key":"ref35","first-page":"13","article-title":"Constraint-based random stimuli generation for hardware verification","volume":"28","author":"naveh","year":"2007","journal-title":"AI Mag"},{"doi-asserted-by":"publisher","key":"ref34","DOI":"10.1109\/DATE.2011.5763252"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/ICFEM.1998.730569"},{"year":"2009","author":"jacob","article-title":"System and method for performing multi-rank command scheduling in DDR SDRAM memory systems","key":"ref40"},{"key":"ref11","doi-asserted-by":"crossref","DOI":"10.1016\/S0065-2458(03)58003-2","article-title":"Bounded model checking","author":"biere","year":"2003","journal-title":"Advances on Computers"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/L-CA.2011.4"},{"year":"2012","author":"chatterjee","article-title":"Usimm: The Utah simulated memory module","key":"ref13"},{"year":"2017","author":"jeong","journal-title":"DrSim A Platform for Flexible DRAM System Research","key":"ref14"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/LCA.2015.2414456"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.2197\/ipsjtsldm.8.63"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1109\/RTAS.2015.7108454"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1145\/342001.339668"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1109\/MICRO.2006.24"},{"key":"ref28","first-page":"1","article-title":"Automated software testing using model-checking","author":"callahan","year":"1996","journal-title":"Proc SPIN Workshop"},{"key":"ref4","first-page":"301","article-title":"Reducing DRAM latencies with an integrated memory hierarchy design","author":"lin","year":"2001","journal-title":"Proc IEEE Int Symp High Perform Comput Archit (HPCA)"},{"doi-asserted-by":"publisher","key":"ref27","DOI":"10.1109\/RTAS.2016.7461341"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/MEMCOD.2008.4547694"},{"key":"ref6","first-page":"32","article-title":"A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality","author":"zhang","year":"2000","journal-title":"Proc ACM\/IEEE Int Symp Microarch (MICRO)"},{"key":"ref29","first-page":"77","article-title":"Testing with model checker: Insuring fault visibility","author":"okun","year":"2003","journal-title":"WSEAS Trans Syst"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"362","DOI":"10.1145\/2989081.2989102","article-title":"DReAM: Dynamic re-arrangement of address mapping to improve the performance of DRAMS","author":"ghasempour","year":"2016","journal-title":"Proc Int Symp Memory Syst (MEMSYS)"},{"key":"ref8","first-page":"19","article-title":"Research problems and opportunities in memory systems","volume":"1","author":"mutlu","year":"2014","journal-title":"Supercomputing Frontiers and Innovations"},{"year":"2015","journal-title":"JEDEC DDR3 SDRAM Specifications Jesd79-3d","key":"ref7"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1145\/1127908.1127991"},{"year":"2017","journal-title":"MCXplore","key":"ref9"},{"year":"2015","journal-title":"Intel platform and component validation a white paper","key":"ref1"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"416","DOI":"10.1145\/2366231.2337207","article-title":"Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems","volume":"40","author":"ausavarungnirun","year":"2012","journal-title":"ACM SIGARCH Comput Archit News"},{"doi-asserted-by":"publisher","key":"ref22","DOI":"10.1145\/2155620.2155624"},{"year":"2012","journal-title":"DDR3 SDRAM Verilog Model","key":"ref21"},{"year":"2017","journal-title":"Intel Xeon Processor","key":"ref42"},{"doi-asserted-by":"publisher","key":"ref24","DOI":"10.1109\/VLSID.2016.88"},{"doi-asserted-by":"publisher","key":"ref41","DOI":"10.1109\/ECRTS.2014.37"},{"year":"2017","author":"podda","journal-title":"Smart Way to Memory Controller Verification Synopsys Memory VIP","key":"ref23"},{"doi-asserted-by":"publisher","key":"ref26","DOI":"10.1109\/MTV.2014.15"},{"doi-asserted-by":"publisher","key":"ref25","DOI":"10.1109\/DTIS.2015.7127364"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/6917053\/07931575.pdf?arnumber=7931575","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T04:38:20Z","timestamp":1643171900000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7931575\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"references-count":42,"URL":"https:\/\/doi.org\/10.1109\/tcad.2017.2705123","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2017]]}}}