{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:00:30Z","timestamp":1740132030979,"version":"3.37.3"},"reference-count":36,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2018,3,1]],"date-time":"2018-03-01T00:00:00Z","timestamp":1519862400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/100007225","name":"Ministry of Science and Technology","doi-asserted-by":"publisher","award":["MOST 104-2628-E-007-003-MY3"],"award-info":[{"award-number":["MOST 104-2628-E-007-003-MY3"]}],"id":[{"id":"10.13039\/100007225","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.1109\/tcad.2017.2712660","type":"journal-article","created":{"date-parts":[[2017,6,6]],"date-time":"2017-06-06T18:35:52Z","timestamp":1496774152000},"page":"657-668","source":"Crossref","is-referenced-by-count":5,"title":["Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability Consideration"],"prefix":"10.1109","volume":"37","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0399-1028","authenticated-orcid":false,"given":"Yixiao","family":"Ding","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chris","family":"Chu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5593-4319","authenticated-orcid":false,"given":"Wai-Kei","family":"Mak","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","first-page":"1","article-title":"Throughput optimization for SADP and e-beam based manufacturing of 1D layout","author":"ding","year":"2014","journal-title":"Proc DAC"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2010.5419806"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629930"},{"key":"ref30","first-page":"844","article-title":"Full-chip routing considering double-via insertion","author":"chen","year":"2006","journal-title":"Proc DAC"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898088"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1093\/comjnl\/10.1.85"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1117\/12.916678"},{"key":"ref10","article-title":"Demonstrating production quality multiple exposure patterning aware routing for the 10nm node","author":"liebmann","year":"2014","journal-title":"Proc SPIE"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1118299.1118376"},{"key":"ref12","article-title":"Yield analysis and optimization","author":"gupta","year":"2010","journal-title":"The Handbook of Algorithms for VLSI Physical Design Automation"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2160916.2160923"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488848"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593176"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2560519.2560530"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744821"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744890"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2842612"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2011.5722266"},{"key":"ref4","first-page":"1","article-title":"An efficient layout decomposition approach for triple patterning lithography","author":"jian","year":"2013","journal-title":"Proc DAC"},{"key":"ref27","first-page":"633","article-title":"Post-routing redundant via insertion and line end extension with via density consideration","author":"lee","year":"2009","journal-title":"Proc ISPD"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228579"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024741"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2005.1466544"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1117\/12.879500"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2160916.2160922"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024901"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105297"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2015.7059085"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1117\/12.793116"},{"key":"ref20","article-title":"Self-aligned double patterning lithography aware detailed routing with color pre-assignment","author":"ding","year":"0","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429408"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228468"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/1353629.1353656"},{"key":"ref23","first-page":"390","article-title":"Non-stitch triple patterning-aware routing based on conflict graph pre-coloring","author":"hsu","year":"2015","journal-title":"Proc ASP DAC"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796524"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1514932.1514960"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/8293876\/07940014.pdf?arnumber=7940014","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:28:12Z","timestamp":1642004892000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7940014\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":36,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2017.2712660","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2018,3]]}}}