{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,28]],"date-time":"2026-03-28T08:48:18Z","timestamp":1774687698272,"version":"3.50.1"},"reference-count":27,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2018,3,1]],"date-time":"2018-03-01T00:00:00Z","timestamp":1519862400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100004164","name":"AnaGlobe, MediaTek, TSMC, MOST of Taiwan","doi-asserted-by":"publisher","award":["MOST 103-2221-E-002-259-MY3"],"award-info":[{"award-number":["MOST 103-2221-E-002-259-MY3"]}],"id":[{"id":"10.13039\/501100004164","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004164","name":"AnaGlobe, MediaTek, TSMC, MOST of Taiwan","doi-asserted-by":"publisher","award":["MOST 103-2812-8-002-003"],"award-info":[{"award-number":["MOST 103-2812-8-002-003"]}],"id":[{"id":"10.13039\/501100004164","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004164","name":"AnaGlobe, MediaTek, TSMC, MOST of Taiwan","doi-asserted-by":"publisher","award":["MOST 104-2221-E-002-132-MY3"],"award-info":[{"award-number":["MOST 104-2221-E-002-132-MY3"]}],"id":[{"id":"10.13039\/501100004164","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004164","name":"AnaGlobe, MediaTek, TSMC, MOST of Taiwan","doi-asserted-by":"publisher","award":["MOST 105-2221-E-002-190-MY3"],"award-info":[{"award-number":["MOST 105-2221-E-002-190-MY3"]}],"id":[{"id":"10.13039\/501100004164","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004164","name":"AnaGlobe, MediaTek, TSMC, MOST of Taiwan","doi-asserted-by":"publisher","award":["MOST 106-2911-I-002-511"],"award-info":[{"award-number":["MOST 106-2911-I-002-511"]}],"id":[{"id":"10.13039\/501100004164","id-type":"DOI","asserted-by":"publisher"}]},{"name":"NTU","award":["NTU-ERP-104R8951"],"award-info":[{"award-number":["NTU-ERP-104R8951"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.1109\/tcad.2017.2712665","type":"journal-article","created":{"date-parts":[[2017,6,6]],"date-time":"2017-06-06T18:35:52Z","timestamp":1496774152000},"page":"669-681","source":"Crossref","is-referenced-by-count":59,"title":["NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints"],"prefix":"10.1109","volume":"37","author":[{"given":"Chau-Chin","family":"Huang","sequence":"first","affiliation":[]},{"given":"Hsin-Ying","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Bo-Qiao","family":"Lin","sequence":"additional","affiliation":[]},{"given":"Sheng-Wei","family":"Yang","sequence":"additional","affiliation":[]},{"given":"Chin-Hao","family":"Chang","sequence":"additional","affiliation":[]},{"given":"Szu-To","family":"Chen","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0564-5719","authenticated-orcid":false,"given":"Yao-Wen","family":"Chang","sequence":"additional","affiliation":[]},{"given":"Tung-Chieh","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Ismail","family":"Bustany","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/43.67789"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.927674"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763100"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2899381"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372613"},{"key":"ref15","article-title":"Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer","author":"naylor","year":"2001"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923063"},{"key":"ref17","first-page":"187","article-title":"A high-quality mixed-size analytical placer considering preplaced blocks and density constraints","author":"chen","year":"2006","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.846366"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055177"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2560519.2565877"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488921"},{"key":"ref3","year":"2009","journal-title":"LEF\/DEF 5 3 to 5 7 Exchange Format"},{"key":"ref6","year":"2017","journal-title":"ISPD 2015 blockage-aware detailed routing-driven placement contest"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228498"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2015.7059034"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2717764.2723572"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2014.7004188"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2717764.2717776"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372612"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055179"},{"key":"ref22","doi-asserted-by":"crossref","first-page":"709","DOI":"10.1109\/TCAD.2012.2235124","article-title":"NCTU-GR 2.0: Multithreaded collision-aware global routing with bounded-length maze routing","volume":"32","author":"liu","year":"2013","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2360453"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687467"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105307"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105309"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1353629.1353640"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/8293876\/07940087.pdf?arnumber=7940087","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:28:12Z","timestamp":1642004892000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7940087\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":27,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2017.2712665","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,3]]}}}