{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,11]],"date-time":"2026-06-11T16:13:23Z","timestamp":1781194403583,"version":"3.54.1"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2018,3,1]],"date-time":"2018-03-01T00:00:00Z","timestamp":1519862400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/OAPA.html"}],"funder":[{"DOI":"10.13039\/100010686","name":"European Commission in the Context of the H2020-FETHPC EXTRA Project","doi-asserted-by":"publisher","award":["671653"],"award-info":[{"award-number":["671653"]}],"id":[{"id":"10.13039\/100010686","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003130","name":"Ph.D. Grant of the Research Foundation Flanders (FWO)","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003130","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.1109\/tcad.2017.2717786","type":"journal-article","created":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T18:27:27Z","timestamp":1497983247000},"page":"629-642","source":"Crossref","is-referenced-by-count":12,"title":["How Preserving Circuit Design Hierarchy During FPGA Packing Leads to Better Performance"],"prefix":"10.1109","volume":"37","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3163-9432","authenticated-orcid":false,"given":"Dries","family":"Vercruyce","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Elias","family":"Vansteenkiste","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Dirk","family":"Stroobandt","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref32","author":"vansteenkiste","year":"2016","journal-title":"FPGA CAD Framework MultiPart and Liquid"},{"key":"ref31","year":"2016","journal-title":"Gaussian Blur GitHub Issue"},{"key":"ref30","year":"2016","journal-title":"LU_Network GitHub Issue"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2006.320013"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1155\/2010\/158602"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2003.159755"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2068716.2068724"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024908"},{"key":"ref15","first-page":"1","article-title":"Yet another many-objective clustering (YAMO-Pack) for FPGA CAD","author":"yang","year":"2013","journal-title":"Proc Int Conf Field Program Logic and Appl"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/378239.378532"},{"key":"ref17","first-page":"262","article-title":"Performance-driven recursive multilevel clustering","author":"dehkordi","year":"2003","journal-title":"Proc IEEE Int Conf Field-Program Technol (FPT)"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.829817"},{"key":"ref19","first-page":"25","article-title":"Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation","author":"marrakchi","year":"2005","journal-title":"Proc ReConFig"},{"key":"ref28","author":"luu","year":"2013","journal-title":"VPR User&#x2019;s Manual (Version 7 0)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/92.820764"},{"key":"ref27","article-title":"hMETIS 1.5: A hypergraph partitioning package","author":"karypis","year":"1998"},{"key":"ref3","article-title":"Multi-threaded deterministic router","author":"jain","year":"2014"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554783"},{"key":"ref29","year":"2016","journal-title":"Sparct2_Core GitHub Issue"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296426"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/605440.605448"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2617593"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344676"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126604001222"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2629579"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2012.6412103"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2007.4380635"},{"key":"ref21","first-page":"31","article-title":"Rent&#x2019;s rule based FPGA packing for routability optimization","author":"feng","year":"2014","journal-title":"Proc ACM\/SIGDA Int Symp Field-Program Gate Arrays"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1971.223159"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577300"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/92.748202"},{"key":"ref25","year":"2016","journal-title":"Stratix IV Device Handbook"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/8293876\/07954038.pdf?arnumber=7954038","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T03:00:32Z","timestamp":1633921232000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7954038\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":32,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2017.2717786","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,3]]}}}