{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T17:00:36Z","timestamp":1774630836058,"version":"3.50.1"},"reference-count":36,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2018,4,1]],"date-time":"2018-04-01T00:00:00Z","timestamp":1522540800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2018,4]]},"DOI":"10.1109\/tcad.2017.2729349","type":"journal-article","created":{"date-parts":[[2017,7,19]],"date-time":"2017-07-19T18:08:27Z","timestamp":1500487707000},"page":"869-882","source":"Crossref","is-referenced-by-count":63,"title":["UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing"],"prefix":"10.1109","volume":"37","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9887-5109","authenticated-orcid":false,"given":"Wuxi","family":"Li","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shounak","family":"Dhar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5705-2501","authenticated-orcid":false,"given":"David Z.","family":"Pan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429539"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691143"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2170567"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593181"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923063"},{"key":"ref35","author":"ahuja","year":"1993","journal-title":"Network Flows Theory Algorithms and Applications"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.870079"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2007.4380635"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.59"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44614-1_58"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065770"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2006.320013"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-63465-7_226"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-30117-2_18"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1142980.1142989"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775984"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.842812"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2980085"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/370155.370567"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2980084"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296426"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1155\/2010\/158602"},{"key":"ref29","year":"2017","journal-title":"ISPD 2016 routability-driven FPGA placement contest"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/605440.605448"},{"key":"ref8","first-page":"25","article-title":"Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation","author":"marrakchi","year":"2005","journal-title":"Proc Int Conf Reconfig Comput FPGAs (ReConFig)"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024908"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1997.606687"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2012.6412103"},{"key":"ref1","year":"2017","journal-title":"Xilinx Inc"},{"key":"ref20","first-page":"555","article-title":"QPF: Efficient quadratic placement for FPGAs","author":"xu","year":"2005","journal-title":"Proc IEEE Int Conf Field Program Logic Appl (FPL)"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2011.02.001"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147033"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488746"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339278"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2980083"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2014.7001421"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/8319545\/07984833.pdf?arnumber=7984833","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:23:34Z","timestamp":1642004614000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7984833\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,4]]},"references-count":36,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2017.2729349","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,4]]}}}