{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,2]],"date-time":"2026-07-02T05:29:08Z","timestamp":1782970148460,"version":"3.54.5"},"reference-count":67,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2018,9,1]],"date-time":"2018-09-01T00:00:00Z","timestamp":1535760000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,9,1]],"date-time":"2018-09-01T00:00:00Z","timestamp":1535760000000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,9,1]],"date-time":"2018-09-01T00:00:00Z","timestamp":1535760000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2018,9,1]],"date-time":"2018-09-01T00:00:00Z","timestamp":1535760000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000185","name":"Defense Advanced Research Projects Agency","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000774","name":"DTRA","doi-asserted-by":"crossref","id":[{"id":"10.13039\/100000774","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2018,9]]},"DOI":"10.1109\/tcad.2017.2752705","type":"journal-article","created":{"date-parts":[[2017,9,15]],"date-time":"2017-09-15T18:41:33Z","timestamp":1505500893000},"page":"1839-1852","source":"Crossref","is-referenced-by-count":19,"title":["Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience)"],"prefix":"10.1109","volume":"37","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8130-2550","authenticated-orcid":false,"given":"Eric","family":"Cheng","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shahrzad","family":"Mirkhani","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Lukasz G.","family":"Szafaryn","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chen-Yong","family":"Cher","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8705-7066","authenticated-orcid":false,"given":"Hyungmin","family":"Cho","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kevin","family":"Skadron","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mircea R.","family":"Stan","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Klas","family":"Lilja","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jacob A.","family":"Abraham","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Pradip","family":"Bose","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5572-5194","authenticated-orcid":false,"given":"Subhasish","family":"Mitra","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/REDW.2015.7336712"},{"key":"ref38","first-page":"1","article-title":"Frequency trends observed in 32nm SOI flip-flops and combinational logic","author":"quinn","year":"2015","journal-title":"IEEE Nucl and Space Radiation Effects Conf"},{"key":"ref33","doi-asserted-by":"crossref","DOI":"10.1145\/2897937.2897996","article-title":"CLEAR: Cross-layer exploration for architecting resilience&#x2014;Combining hardware and software techniques to tolerate soft errors in processor cores","author":"cheng","year":"2016","journal-title":"Proc 53rd Annu Design Autom Conf"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.44"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250719"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2012.2192736"},{"key":"ref37","first-page":"1","article-title":"SER prediction in advanced finFET and SOI finFET technologies; challenges and comparisons to measurements","author":"lilja","year":"2016","journal-title":"Single Event Effects (SEE) Symp"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2013.2273437"},{"key":"ref35","year":"2017","journal-title":"Synopsys design suite"},{"key":"ref34","first-page":"1","article-title":"An analytical model for hardened latch selection and exploration","author":"sullivan","year":"2016","journal-title":"Proc 2nd Workshop Silicon Errors Logic-Syst Effects (SELSE)"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346195"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2005.70"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2005.82"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.887832"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2008.4630080"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1080\/00031305.2016.1154108"},{"key":"ref27","article-title":"BEE3: Revitalizing computer architecture research","author":"davis","year":"2009"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2015.7116254"},{"key":"ref66","year":"2017","journal-title":"Leon3 Processor"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2004.1311877"},{"key":"ref67","article-title":"Tolerating soft errors in processor cores using CLEAR (cross-layer exploration for architecting resilience","author":"cheng","year":"2017","journal-title":"arXiv 1709 09921 [cs AR]"},{"key":"ref2","first-page":"5","article-title":"Toward exascale resilience: 2014 update","volume":"1","author":"cappello","year":"2014","journal-title":"Supercomputing Frontiers and Innovations"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.110"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744923"},{"key":"ref22","first-page":"1","author":"barker","year":"2013","journal-title":"PERFECT (Power Efficiency Revolution For Embedded Computing Technologies) Benchmark Suite Manual"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/2.869367"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2014.6861096"},{"key":"ref23","first-page":"1","article-title":"CLEAR: Cross-layer exploration for architecting resilience: Combining hardware and software techniques to tolerate soft errors in processor cores","author":"cheng","year":"2016","journal-title":"Proc 53rd Annu Design Autom Conf"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488859"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1147\/rd.523.0275"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/24.994926"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/AERO.2002.1035377"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/12.54836"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1984.1676475"},{"key":"ref57","first-page":"115","article-title":"Numerically stable real number codes based on random matrices","author":"chen","year":"2005","journal-title":"Proc 5th Int Conf Comput Sci (ICCS)"},{"key":"ref56","doi-asserted-by":"crossref","first-page":"410","DOI":"10.1016\/j.jpdc.2008.12.002","article-title":"Algorithm-based fault tolerance applied to high performance computing","volume":"69","author":"bosilca","year":"2009","journal-title":"J Parallel Distrib Comput"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2341894"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2009.23"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2334301"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/24.994913"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.859577"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1147\/JRD.2011.2127330","article-title":"IBM POWER7 multicore server processor","volume":"55","author":"sinharoy","year":"2011","journal-title":"IBM J Res Develop"},{"key":"ref40","first-page":"1","article-title":"32nm SOI SRAM and latch SEU cross-sections measured (heavy ion data) and determined with simulations","author":"turowski","year":"2015","journal-title":"Single Event Effects (SEE) Symp"},{"key":"ref12","first-page":"1","article-title":"The resilience wall: Cross-layer solution strategies","author":"mitra","year":"2014","journal-title":"Proc Tech Prog -Int Symp VLSI Technol Syst Appl (VLSI-TSA)"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2010.5488831"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2012.2218128"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2015.2495130"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2013.2288782"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2014.6946138"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2009.5173251"},{"key":"ref19","first-page":"203","article-title":"LEAP: Layout design through error-aware transistor positioning for soft-error resilient sequential cell design","author":"kelin","year":"2010","journal-title":"Proc IEEE Int Rel Phys Symp (IRPS)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5456959"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5456960"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2596683"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2014.6860584"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1982.1676066"},{"key":"ref7","author":"pedram","year":"2012","journal-title":"Report for the NSF Workshop on cross-layer power optimization and management"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2008.4630072"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2003.1234286"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.18"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894311"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2012.6263960"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1999.809458"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2089657"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007148"},{"key":"ref44","article-title":"Effects of single-event-induced charge sharing in sub-100 nm bulk CMOS technologies","author":"amusan","year":"2009"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1147\/rd.435.0863"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielaam\/43\/8440579\/8038842-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/8440579\/08038842.pdf?arnumber=8038842","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,8]],"date-time":"2022-04-08T18:47:46Z","timestamp":1649443666000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8038842\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,9]]},"references-count":67,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2017.2752705","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,9]]}}}