{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,2]],"date-time":"2026-06-02T23:58:32Z","timestamp":1780444712984,"version":"3.54.1"},"reference-count":52,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2018,9,1]],"date-time":"2018-09-01T00:00:00Z","timestamp":1535760000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61631002"],"award-info":[{"award-number":["61631002"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61504007"],"award-info":[{"award-number":["61504007"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61427803"],"award-info":[{"award-number":["61427803"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2018,9]]},"DOI":"10.1109\/tcad.2017.2772817","type":"journal-article","created":{"date-parts":[[2017,11,13]],"date-time":"2017-11-13T19:08:50Z","timestamp":1510600130000},"page":"1867-1880","source":"Crossref","is-referenced-by-count":88,"title":["Secure Scan and Test Using Obfuscation Throughout Supply Chain"],"prefix":"10.1109","volume":"37","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7943-8360","authenticated-orcid":false,"given":"Xiaoxiao","family":"Wang","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Dongrong","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2147-7751","authenticated-orcid":false,"given":"Miao","family":"He","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4852-0569","authenticated-orcid":false,"given":"Donglin","family":"Su","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mark","family":"Tehranipoor","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","first-page":"2","article-title":"Optical fault induction attacks","author":"skorobogatov","year":"2002","journal-title":"Proc Workshop Cryptographic Hardware Embedded Syst"},{"key":"ref38","first-page":"513","article-title":"Differential fault analysis of secret key cryptosystems","author":"biham","year":"1997","journal-title":"Proc Annu Int Cryptol Conf"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2016.2613847"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2016.7538900"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2007.89"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2011.85"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2017.7858392"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.9"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ADCOM.2007.110"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2007.70215"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2006.7"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISOCC.2012.6407063"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2009.20"},{"key":"ref2","author":"tehranipoor","year":"2011","journal-title":"Introduction to Hardware Security and Trust"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2014.6847798"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2012.6231061"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2274619"},{"key":"ref21","first-page":"19","article-title":"Scan attacks and countermeasures in presence of scan response compactors","author":"da rolt","year":"2011","journal-title":"Proc IEEE European Test Symp (ETS)"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2009.15"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2017.7968248"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.906483"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2011.5722303"},{"key":"ref50","first-page":"1","article-title":"Fault attacks on secure chips: From glitch to flash","author":"skorobogatov","year":"2011","journal-title":"Design and Security of Cryptographic Algorithms and Devices (ECRYPT II)"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2009.5225058"},{"key":"ref52","article-title":"Memory with a bit line block and\/or a word line block for preventing reverse engineering","author":"clark","year":"2002"},{"key":"ref10","article-title":"Exploiting the scan side channel for reverse engineering of a VLSI device","author":"azriel","year":"2016"},{"key":"ref11","first-page":"219","article-title":"Scan design and secure chip [secure IC testing]","volume":"4","author":"hely","year":"2004","journal-title":"Proc IOLTS"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/2505014"},{"key":"ref12","first-page":"9","article-title":"Design principles for tamper-resistant smartcard processors","volume":"99","author":"k\u00f6mmerling","year":"1999","journal-title":"Proc USENIX Workshop Smartcard Technol"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2006.55"},{"key":"ref14","first-page":"1","article-title":"IEEE 1500 compatible secure test wrapper for embedded IP cores","author":"chiu","year":"2008","journal-title":"Proc IEEE Int Test Conf (ITC)"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2208209"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2013.6604085"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2013.6673281"},{"key":"ref18","first-page":"461","article-title":"Effects of embedded decompression and compaction architectures on side-channel attack resistance","author":"liu","year":"2007","journal-title":"Proc VTS"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2014.7035357"},{"key":"ref4","first-page":"1","article-title":"Dynamically obfuscated scan for protecting IPs against scan-based attacks throughout supply chain","author":"zhang","year":"2017","journal-title":"Proc IEEE VLSI Test Symp (VTS)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2015.7116256"},{"key":"ref6","first-page":"339","article-title":"Scan based side channel attack on dedicated hardware implementations of data encryption standard","author":"yang","year":"2004","journal-title":"Proc Int Test Conf (ITC)"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2005.42"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.862745"},{"key":"ref7","first-page":"407","article-title":"Scan-based attack against elliptic curve cryptosystems","author":"nara","year":"2010","journal-title":"Proc Asia South Pacific Design Automat Conf"},{"key":"ref49","year":"2016","journal-title":"Synopsys 32\/28nm Generic Library"},{"key":"ref9","first-page":"2481","article-title":"Scan-based side-channel attack against rsa cryptosystems using scan signatures","volume":"93","author":"ryuta","year":"2010","journal-title":"IEICE Trans Fundam Electron Commun Comput Sci"},{"key":"ref46","year":"2017","journal-title":"AMD Memory Encryption"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691207"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2008.28"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147015"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2016.243"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2005.58"},{"key":"ref44","first-page":"1","article-title":"Diffusion programmable device: The device to prevent reverse engineering","volume":"2014","author":"shiozaki","year":"2014","journal-title":"IACR Cryptology ePrint"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-44318-8"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/8440579\/08105900.pdf?arnumber=8105900","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T12:19:33Z","timestamp":1643199573000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8105900\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,9]]},"references-count":52,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2017.2772817","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,9]]}}}