{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,17]],"date-time":"2025-09-17T16:13:26Z","timestamp":1758125606111,"version":"3.37.3"},"reference-count":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T00:00:00Z","timestamp":1538352000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T00:00:00Z","timestamp":1538352000000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T00:00:00Z","timestamp":1538352000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T00:00:00Z","timestamp":1538352000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF 1314876","CCF 1514206"],"award-info":[{"award-number":["CCF 1314876","CCF 1514206"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1109\/tcad.2017.2772822","type":"journal-article","created":{"date-parts":[[2017,11,13]],"date-time":"2017-11-13T19:08:50Z","timestamp":1510600130000},"page":"2064-2075","source":"Crossref","is-referenced-by-count":13,"title":["Profit: &lt;underline&gt;Pr&lt;\/underline&gt;iority and P&lt;underline&gt;o&lt;\/underline&gt;wer\/Per&lt;underline&gt;f&lt;\/underline&gt;ormance Opt&lt;underline&gt;i&lt;\/underline&gt;miza&lt;underline&gt;t&lt;\/underline&gt;ion for Many-Core Systems"],"prefix":"10.1109","volume":"37","author":[{"given":"Zhuo","family":"Chen","sequence":"first","affiliation":[]},{"given":"Dimitrios","family":"Stamoulis","sequence":"additional","affiliation":[]},{"given":"Diana","family":"Marculescu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"crossref","first-page":"347","DOI":"10.1145\/512274.512284","article-title":"Algorithm 232: Heapsort","volume":"7","author":"williams","year":"1964","journal-title":"Commun ACM"},{"key":"ref32","first-page":"189","article-title":"Economic learning for thermal-aware power budgeting in many-core architectures","author":"ebi","year":"2011","journal-title":"Proceedings of Intl Conf on CODES & ISSS"},{"key":"ref31","first-page":"1","article-title":"Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation","author":"carlson","year":"2011","journal-title":"Proc Int Conf High Perform Comput Netw Stor Anal (SC)"},{"key":"ref30","first-page":"469","article-title":"McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures","author":"li","year":"2009","journal-title":"Proc of the 42nd MICRO"},{"key":"ref10","first-page":"602","article-title":"Enhanced Q-learning algorithm for dynamic power management with performance constraint","author":"liu","year":"2010","journal-title":"Proc DATE"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"461","DOI":"10.1145\/1687399.1687486","article-title":"Adaptive power management using reinforcement learning","author":"tan","year":"2009","journal-title":"Proc ICCAD"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333686"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2629486"},{"key":"ref14","first-page":"747","article-title":"Dynamic power management using machine learning","author":"dhiman","year":"2006","journal-title":"Proc ICCAD"},{"key":"ref15","first-page":"178","article-title":"Improving the efficiency of power management techniques by using Bayesian classification","author":"jung","year":"2008","journal-title":"Proc ISQED"},{"key":"ref16","first-page":"318","article-title":"Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach","author":"bitirgen","year":"2008","journal-title":"Proc MICRO"},{"key":"ref17","first-page":"1","article-title":"Learning the optimal operating point for many-core systems with extended range voltage\/frequency scaling","author":"juan","year":"2013","journal-title":"Proc CODES-ISSS"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1394608.1382152"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2811404"},{"key":"ref28","first-page":"57","article-title":"Efficient reliability analysis of processor datapath using atomistic BTI variability models","author":"stamoulis","year":"2015","journal-title":"Proc GLSVSLI"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155641"},{"key":"ref27","doi-asserted-by":"crossref","first-page":"308","DOI":"10.1145\/2934583.2934641","article-title":"Can we guarantee performance requirements under workload and process variations?","author":"stamoulis","year":"2016","journal-title":"Proc Int Symp Low Power Electron Design (ISLPED)"},{"key":"ref3","first-page":"77","article-title":"Dynamic power-performance adaptation of parallel computation on chip multiprocessors","author":"li","year":"2006","journal-title":"Proc HPCA"},{"key":"ref6","first-page":"29","article-title":"Scalable thread scheduling and global power management for heterogeneous many-core architectures","author":"winter","year":"2010","journal-title":"Proc PACT"},{"key":"ref29","first-page":"1","article-title":"Exploring aging deceleration in FinFET-based multi-core systems","author":"cai","year":"2016","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design (ICCAD)"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"38","DOI":"10.1145\/1283780.1283790","article-title":"Analysis of dynamic voltage\/frequency scaling in chip-multiprocessors","author":"herbert","year":"2007","journal-title":"Proc ISLPED"},{"key":"ref8","first-page":"1556","article-title":"Distributed peak power management for many-core architectures","author":"sartori","year":"2009","journal-title":"Proc DATE"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555794"},{"key":"ref2","first-page":"54","article-title":"Dynamic thread mapping for high-performance, power-efficient heterogeneous many-core systems","author":"liu","year":"2013","journal-title":"Proc ICCD"},{"key":"ref9","first-page":"431","article-title":"Power token balancing: Adapting CMPS to power constraints for parallel multithreaded workloads","author":"cebri\u00e1n","year":"2011","journal-title":"Proc IPDPS"},{"key":"ref1","first-page":"347","article-title":"An analysis of efficient multi-core global power management policies: Maximizing performance for a given power budget","author":"isci","year":"2006","journal-title":"Proc MICRO"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1785481.1785553"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2077830"},{"key":"ref21","first-page":"1","article-title":"A distributed and self-calibrating model-predictive controller for energy and thermal management of high-performance multicores","author":"bartolini","year":"2011","journal-title":"Proc DATE"},{"journal-title":"Reinforcement Learning An Introduction","year":"1998","author":"barto","key":"ref24"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2504330"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/BF00992698"},{"key":"ref25","doi-asserted-by":"crossref","first-page":"1521","DOI":"10.7873\/DATE.2015.0992","article-title":"Distributed Reinforcement Learning for Power Limited Many-Core System Performance Optimization","author":"zhuo chen","year":"2015","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielaam\/43\/8467416\/8105861-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/8467416\/08105861.pdf?arnumber=8105861","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,8,28]],"date-time":"2023-08-28T12:35:48Z","timestamp":1693226148000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8105861\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":33,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2017.2772822","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2018,10]]}}}