{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,9]],"date-time":"2026-07-09T05:07:54Z","timestamp":1783573674040,"version":"3.55.0"},"reference-count":54,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T00:00:00Z","timestamp":1538352000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T00:00:00Z","timestamp":1538352000000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T00:00:00Z","timestamp":1538352000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T00:00:00Z","timestamp":1538352000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Key Research and Development Program of China","doi-asserted-by":"crossref","award":["2016YFB1000303"],"award-info":[{"award-number":["2016YFB1000303"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100012166","name":"National Key Research and Development Program of China","doi-asserted-by":"crossref","award":["2016YFB0201800"],"award-info":[{"award-number":["2016YFB0201800"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Joint Research Fund for Overseas Chinese, Hong Kong and Macau Young Scientists of the National Natural Science Foundation of China","award":["61628210"],"award-info":[{"award-number":["61628210"]}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["91630206"],"award-info":[{"award-number":["91630206"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61672423"],"award-info":[{"award-number":["61672423"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61772092"],"award-info":[{"award-number":["61772092"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1718080"],"award-info":[{"award-number":["CCF-1718080"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"name":"National 863 Program","award":["2015AA015304"],"award-info":[{"award-number":["2015AA015304"]}]},{"DOI":"10.13039\/501100004543","name":"China Scholarship Council","doi-asserted-by":"publisher","award":["201606280098"],"award-info":[{"award-number":["201606280098"]}],"id":[{"id":"10.13039\/501100004543","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1109\/tcad.2017.2782765","type":"journal-article","created":{"date-parts":[[2017,12,13]],"date-time":"2017-12-13T19:20:12Z","timestamp":1513192812000},"page":"1957-1970","source":"Crossref","is-referenced-by-count":29,"title":["ApproxFTL: On the Performance and Lifetime Improvement of 3-D NAND Flash-Based SSDs"],"prefix":"10.1109","volume":"37","author":[{"given":"Jinhua","family":"Cui","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Youtao","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Liang","family":"Shi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chun Jason","family":"Xue","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Weiguo","family":"Wu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jun","family":"Yang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","first-page":"1","article-title":"The multi-streamed solid-state drive","author":"kang","year":"2014","journal-title":"Proc of HotStorage"},{"key":"ref38","first-page":"1","year":"2007","journal-title":"Stress-Test-Driven Qualification of Integrated Circuits"},{"key":"ref33","first-page":"1","article-title":"Improving NAND endurance by dynamic program and erase scaling","author":"jeong","year":"2013","journal-title":"Proc of HotStorage"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2014.2354931"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/1508284.1508271"},{"key":"ref30","first-page":"77","article-title":"CAFTL: A content-aware flash translation layer enhancing the lifespan of flash memory based solid state drives","volume":"11","author":"chen","year":"2011","journal-title":"Proc FAST"},{"key":"ref37","first-page":"9","article-title":"Bit error rate in NAND flash memories","author":"mielke","year":"2008","journal-title":"Proc IEEE Int Rel Phys Symp (IRPS)"},{"key":"ref36","first-page":"245","article-title":"Exploiting memory device wear-out dynamics to improve NAND flash memory system performance","volume":"11","author":"pan","year":"2011","journal-title":"Proc FAST"},{"key":"ref35","first-page":"46","article-title":"An 8 Gb multi-level NAND flash memory with 63 nm STI CMOS process technology","author":"byeon","year":"2005","journal-title":"IEEE Int Solid State Circuits Conf Dig Tech Papers (ISSCC)"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2453369"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2011.67"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2009.5373762"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2011.6131148"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2016.2520965"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-94-017-7512-0"},{"key":"ref20","first-page":"49","article-title":"Vulnerabilities in MLC NAND flash memory programming: Experimental analysis, exploits, and mitigation techniques","author":"cai","year":"2017","journal-title":"Proc IEEE Int Symp High Perform Comput Archit (HPCA)"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/1993498.1993518"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2248487.1950391"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2954679.2872413"},{"key":"ref23","doi-asserted-by":"crossref","first-page":"301","DOI":"10.1145\/2248487.2151008","article-title":"Architecture support for disciplined approximate programming","volume":"47","author":"esmaeilzadeh","year":"2012","journal-title":"ACM SIGPLAN Notices"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750371"},{"key":"ref25","first-page":"361","article-title":"Approximate storage of compressed and encrypted videos","author":"jevdjic","year":"2017","journal-title":"Proc Int Conf Archit Support Program Lang Oper Syst"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/CODES-ISSS.2013.6658994"},{"key":"ref51","doi-asserted-by":"crossref","first-page":"96","DOI":"10.1145\/1995896.1995912","article-title":"Performance impact and interplay of SSD parallelism through advanced commands, allocation strategy and data granularity","author":"hu","year":"2011","journal-title":"Proc Int Conf Supercomput"},{"key":"ref54","first-page":"113","article-title":"Analysis and characterization of inherent application resilience for approximate computing","author":"chippa","year":"2013","journal-title":"Proc 50th Annu Design Autom Conf"},{"key":"ref53","first-page":"1","article-title":"Achieving page-mapping FTL performance at block-mapping FTL cost by hiding address translation","author":"hu","year":"2010","journal-title":"Proc IEEE 26th Symp Mass Stor Syst Technol (MSST)"},{"key":"ref52","first-page":"1","article-title":"7.2 a 128Gb 3b\/cell V-NAND flash memory with 1Gb\/s I\/O rate","author":"im","year":"2015","journal-title":"Proc IEEE Int Solid State Circuits Conf (ISSCC)"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2007.4339708"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2604297"},{"key":"ref40","first-page":"79","article-title":"The harey tortoise: Managing heterogeneous write performance in SSDs","author":"grupp","year":"2013","journal-title":"Proc USENIX Annu Tech Conf"},{"key":"ref12","first-page":"188","article-title":"Multi-layered vertical gate NAND flash overcoming stacking limit for terabit density storage","author":"kim","year":"2009","journal-title":"Proc Symp VLSI Technol"},{"key":"ref13","first-page":"1","article-title":"Overview of 3D NAND flash and progress of vertical gate (VG) architecture","author":"lue","year":"2012","journal-title":"Proc IEEE 11th Int Conf Solid State Integr Circuit Technol (ICSICT)"},{"key":"ref14","first-page":"156t","article-title":"Study of the interference and disturb mechanisms of split-page 3D vertical gate (VG) NAND flash and optimized programming algorithms for multi-level cell (MLC) storage","author":"hsieh","year":"2013","journal-title":"Proc Symp VLSI Technol (VLSIT)"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2253812"},{"key":"ref16","first-page":"22","article-title":"A light-weighted software-controlled cache for PCM-based main memory systems","author":"chang","year":"2015","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design (ICCAD)"},{"key":"ref17","first-page":"123","article-title":"Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation","author":"cai","year":"2013","journal-title":"Proc IEEE 31st Int Conf Comput Design (ICCD)"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"264","DOI":"10.1109\/55.998871","article-title":"Effects of floating-gate interference on NAND flash memory cell operation","volume":"23","author":"lee","year":"2002","journal-title":"IEEE Electron Device Lett"},{"key":"ref19","first-page":"521","article-title":"Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis","author":"cai","year":"2012","journal-title":"Proc Conf Design Autom Test Europe"},{"key":"ref4","first-page":"68","article-title":"A highly scalable vertical gate (VG) 3D NAND flash with robust program disturb immunity using a novel PN diode decoding structure","author":"hung","year":"2011","journal-title":"Proc Symp VLSI Technol (VLSIT)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2013.2247606"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2451660"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2288687"},{"key":"ref8","first-page":"1","article-title":"A disturbance-aware sub-block design to improve reliability of 3D MLC flash memory","author":"chang","year":"2016","journal-title":"Proc IEEE\/ACM\/IFIP Int Conf Hardw -Softw Codes Syst Synt"},{"key":"ref7","first-page":"479","article-title":"On relaxing page program disturbance over 3D MLC flash memory","author":"chang","year":"2015","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design (ICCAD)"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1145\/2950059"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2644808"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/MSST.2014.6855549"},{"key":"ref45","first-page":"47","article-title":"Wear unleveling: Improving NAND flash lifetime by balancing page endurance","volume":"14","author":"jimenez","year":"2014","journal-title":"Proc FAST"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2595572"},{"key":"ref47","first-page":"1","article-title":"WARM: Improving NAND flash memory lifetime with write-hotness aware retention management","author":"luo","year":"2015","journal-title":"Proc 31st Symp Mass Storage Syst Technol (MSST)"},{"key":"ref42","first-page":"257","article-title":"Write once, get 50% free: Saving SSD erase costs using WOM codes","author":"yadgar","year":"2015","journal-title":"Proc FAST"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2393299"},{"key":"ref44","first-page":"428","article-title":"Hybrid solid-state disks: Combining heterogeneous NAND flash in large SSDs","author":"chang","year":"2008","journal-title":"Proc IEEE Asia South Pacific Design Autom Conf (ASPDAC)"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2010.09.005"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielaam\/43\/8467416\/8194861-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/8467416\/08194861.pdf?arnumber=8194861","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,8,10]],"date-time":"2022-08-10T12:49:18Z","timestamp":1660135758000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8194861\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":54,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2017.2782765","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,10]]}}}