{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,11]],"date-time":"2026-04-11T13:21:05Z","timestamp":1775913665995,"version":"3.50.1"},"reference-count":43,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2018,12,1]],"date-time":"2018-12-01T00:00:00Z","timestamp":1543622400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"EU COST Action","award":["IC1401"],"award-info":[{"award-number":["IC1401"]}]},{"DOI":"10.13039\/501100000266","name":"Engineering and Physical Sciences Research Council","doi-asserted-by":"publisher","award":["EP\/K017829\/1"],"award-info":[{"award-number":["EP\/K017829\/1"]}],"id":[{"id":"10.13039\/501100000266","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2018,12]]},"DOI":"10.1109\/tcad.2018.2791468","type":"journal-article","created":{"date-parts":[[2018,1,9]],"date-time":"2018-01-09T22:05:02Z","timestamp":1515535502000},"page":"3151-3162","source":"Crossref","is-referenced-by-count":95,"title":["A Data-Driven Verilog-A ReRAM Model"],"prefix":"10.1109","volume":"37","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4286-6553","authenticated-orcid":false,"given":"Ioannis","family":"Messaris","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8034-2398","authenticated-orcid":false,"given":"Alexander","family":"Serb","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0833-6209","authenticated-orcid":false,"given":"Spyros","family":"Stathopoulos","sequence":"additional","affiliation":[]},{"given":"Ali","family":"Khiat","sequence":"additional","affiliation":[]},{"given":"Spyridon","family":"Nikolaidis","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6267-6909","authenticated-orcid":false,"given":"Themistoklis","family":"Prodromakis","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","article-title":"Verilog—A for memristor models","author":"kvatinsky","year":"2011"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2492421"},{"key":"ref33","year":"2017","journal-title":"Eureqa Nutonian"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1088\/0143-0807\/30\/4\/001"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1021\/acsami.6b04919"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2017.8050789"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2013.2291158"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5937942"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1371\/journal.pone.0120506"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2017.8050398"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2433536"},{"key":"ref40","first-page":"945","article-title":"Reliable SPICE simulations of memristors, memcapacitors and meminductors","volume":"22","author":"biolek","year":"2013","journal-title":"Radioengineering"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2252057"},{"key":"ref12","first-page":"10","article-title":"Memristive synapses are becoming reality","author":"laiho","year":"2010","journal-title":"The Neuromorphic Engineer"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/s00339-011-6296-1"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1063\/1.1702682"},{"key":"ref15","first-page":"210","article-title":"SPICE model of memristor withnonlinear dopant drift","volume":"18","author":"biolek","year":"2009","journal-title":"Radioengineering"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2158004"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2215714"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2013.2293354"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2016.2545412"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2190563"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2015.2414423"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/25\/16\/165202"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006439"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1039\/c3nr01176c"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1038\/ncomms12805"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1049\/el.2010.2716"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1038\/ncomms12611"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2478491"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCT.1971.1083337"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1038\/ncomms8522"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"80","DOI":"10.1038\/nature06932","article-title":"The missing memristor found","volume":"453","author":"strukov","year":"2008","journal-title":"Nature"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2433676"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/22\/25\/254023"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1038\/srep10150"},{"key":"ref42","first-page":"392","year":"2009","journal-title":"Verilog-AMS Language Reference Manual"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1063\/1.4809530"},{"key":"ref41","author":"messaris","year":"2017","journal-title":"Dataset for a Computationally Efficient Verilog—A ReRAM Model (V 2)"},{"key":"ref23","article-title":"Investigation and manipulation of different analog behaviors of memristor as electronic synapse for neuromorphic applications","volume":"6","author":"wang","year":"2016","journal-title":"Sci Rep"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-39531-9_2"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/22\/25\/254001"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1021\/nl904092h"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/8540963\/08252766.pdf?arnumber=8252766","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,27]],"date-time":"2022-01-27T02:40:17Z","timestamp":1643251217000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8252766\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,12]]},"references-count":43,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2018.2791468","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,12]]}}}