{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T19:49:47Z","timestamp":1771703387466,"version":"3.50.1"},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2018,12,1]],"date-time":"2018-12-01T00:00:00Z","timestamp":1543622400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/100002418","name":"Intel Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100002418","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100009011","name":"Ontario Centres of Excellence","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100009011","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100000038","name":"Natural Sciences and Engineering Research Council of Canada","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100000038","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Canadian Foundation for Innovation"},{"name":"Ontario Research Fund"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2018,12]]},"DOI":"10.1109\/tcad.2018.2801222","type":"journal-article","created":{"date-parts":[[2018,2,2]],"date-time":"2018-02-02T19:20:35Z","timestamp":1517599235000},"page":"3095-3108","source":"Crossref","is-referenced-by-count":9,"title":["Automatic Application-Specific Calibration to Enable Dynamic Voltage Scaling in FPGAs"],"prefix":"10.1109","volume":"37","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2696-3086","authenticated-orcid":false,"given":"Ibrahim","family":"Ahmed","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6990-046X","authenticated-orcid":false,"given":"Shuze","family":"Zhao","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7416-1320","authenticated-orcid":false,"given":"Olivier","family":"Trescases","sequence":"additional","affiliation":[]},{"given":"Vaughn","family":"Betz","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2014.32"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/2617593"},{"key":"ref31","article-title":"Logic synthesis and optimization benchmarks user guide 3.0","author":"yang","year":"1991"},{"key":"ref30","first-page":"354","article-title":"A new way of detecting reconvergent fanout branch pairs in logic circuits","author":"xu","year":"2004","journal-title":"Proc 13th Asian Test Symp"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/APEC.2017.7931114"},{"key":"ref34","year":"2016","journal-title":"Gurobi Optimizer Reference Manual"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2012.27"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645598"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554784"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2513683.2513689"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2392616.2392618"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2017.04.021"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966717"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882503"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271113"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/OLT.2002.1030195"},{"key":"ref28","doi-asserted-by":"crossref","first-page":"59","DOI":"10.1145\/360276.360299","article-title":"Using sparse crossbars within LUT clusters","author":"lemieux","year":"2001","journal-title":"Proc FPGA"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2012.6412136"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.824300"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/APEC.2016.7468125"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2011.5770808"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1049\/ip-e.1987.0019"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577342"},{"key":"ref8","year":"2015","journal-title":"AN 711 Power Reduction Features in Arria 10"},{"key":"ref7","first-page":"396","article-title":"Characterizing process variation in nanometer CMOS","author":"agarwal","year":"2007","journal-title":"Proc DAC"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2005.1568543"},{"key":"ref1","first-page":"398","article-title":"A distributed critical-path timing monitor for a 65nm high-performance microprocessor","author":"drake","year":"2007","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.855955"},{"key":"ref22","year":"2014","journal-title":"Cyclone IV Device Handbook"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645511"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2014.31"},{"key":"ref23","year":"2009","journal-title":"Quartus-II University Interface Program"},{"key":"ref26","first-page":"12","article-title":"The stratix™ routing and logic architecture","author":"lewis","year":"2003","journal-title":"Proc FPGA"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2435264.2435281"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/8540963\/08279472.pdf?arnumber=8279472","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,8,31]],"date-time":"2023-08-31T20:54:06Z","timestamp":1693515246000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8279472\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,12]]},"references-count":35,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2018.2801222","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,12]]}}}