{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T16:05:47Z","timestamp":1781885147156,"version":"3.54.5"},"reference-count":62,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2019,3]]},"DOI":"10.1109\/tcad.2018.2812118","type":"journal-article","created":{"date-parts":[[2018,3,15]],"date-time":"2018-03-15T20:44:34Z","timestamp":1521146674000},"page":"466-479","source":"Crossref","is-referenced-by-count":29,"title":["An Efficient SRAM-Based Reconfigurable Architecture for Embedded Processors"],"prefix":"10.1109","volume":"38","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8092-2969","authenticated-orcid":false,"given":"Sajjad","family":"Tamimi","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5133-3046","authenticated-orcid":false,"given":"Zahra","family":"Ebrahimi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3655-0501","authenticated-orcid":false,"given":"Behnam","family":"Khaleghi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0264-3865","authenticated-orcid":false,"given":"Hossein","family":"Asadi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","first-page":"199","article-title":"A 45nm 1.3 GHz 16.7 double-precision GFLOPS\/W RISC-V processor with vector accelerators","author":"lee","year":"2014","journal-title":"Proc IEEE European Solid-State Circuits Conf (ESSCIRC)"},{"key":"ref38","year":"2017","journal-title":"VectorBlox Computing Inc"},{"key":"ref33","first-page":"230","article-title":"Benchmarking method and designs targeting logic synthesis for FPGAs","volume":"7","author":"pistorius","year":"2007","journal-title":"Proc IWLS"},{"key":"ref32","year":"2011","journal-title":"ABC A System for Sequential Synthesis and Verification Release 70901"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/WWC.2001.990739"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887921"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2011.2182009"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927503"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/2617593"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2017.8280115"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446050"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.23919\/FPL.2017.8056807"},{"key":"ref61","year":"2017","journal-title":"Opencores"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2005774"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1013235.1013249"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2393914"},{"key":"ref2","author":"marwedel","year":"2010","journal-title":"Embedded System Design Embedded Systems Foundations of Cyber-physical Systems"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/54.350695"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/12.859540"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/2.839324"},{"key":"ref21","doi-asserted-by":"crossref","first-page":"61","DOI":"10.1007\/978-3-540-45234-8_7","article-title":"ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix","author":"mei","year":"2003","journal-title":"Field Programmable Logic and Application"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2000.854393"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1142980.1142986"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2007.4380649"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/360276.360328"},{"key":"ref50","year":"2008","journal-title":"Virtex-II Platform FPGA User Guide"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1002\/9781118958254"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1145\/1777401.1777403"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.909795"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2344051"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"ref55","year":"2016","journal-title":"RTEMS Cross Compilation System (RCC)"},{"key":"ref54","first-page":"1342","article-title":"A power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon era","author":"seifoori","year":"2017","journal-title":"Proc Conf Design Autom Test Europe"},{"key":"ref53","author":"sharp","year":"2017","journal-title":"Power Management Solution Guide–Xilinx"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145737"},{"key":"ref10","year":"2016","journal-title":"OpenRT website"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2005.209"},{"key":"ref40","first-page":"22","article-title":"Cacti 6.0: A tool to model large caches","author":"muralimanohar","year":"2009"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.154"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICM.2006.373294"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1086297.1086325"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228584"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2010.5681533"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2024723.2000108"},{"key":"ref18","first-page":"335","article-title":"Exploiting STT-NV technology for reconfigurable, high performance, low power, and low temperature functional unit design","author":"ashammagari","year":"2014","journal-title":"Proc Conf Design Autom Test Europe"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2591513.2591535"},{"key":"ref4","volume":"317","author":"marwedel","year":"2013","journal-title":"Code Generation for Embedded Processors"},{"key":"ref3","author":"barr","year":"1999","journal-title":"Programming Embedded Systems in C and C++"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1165573.1165623"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"},{"key":"ref8","article-title":"Instruction sets should be free: The case for RISC-V","author":"asanovi?","year":"2014"},{"key":"ref7","year":"2016","journal-title":"Gaisler Research"},{"key":"ref49","year":"2011","journal-title":"Stratix-2 Platform FPGA Hand Book"},{"key":"ref9","year":"2016","journal-title":"OpenSparc Website"},{"key":"ref46","year":"2016","journal-title":"Behavioural Simulation (Spike)"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2636141"},{"key":"ref48","year":"2016","journal-title":"Nangate open cell library"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.243959"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.824300"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950419"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927504"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2015.7293953"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/8643655\/08316989.pdf?arnumber=8316989","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T21:14:52Z","timestamp":1657746892000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8316989\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,3]]},"references-count":62,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2018.2812118","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,3]]}}}