{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,10]],"date-time":"2026-01-10T18:51:49Z","timestamp":1768071109531,"version":"3.49.0"},"reference-count":41,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100007350","name":"Consejo Nacional de Ciencia y Tecnolog\u00eda","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100007350","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2019,4]]},"DOI":"10.1109\/tcad.2018.2834403","type":"journal-article","created":{"date-parts":[[2018,5,8]],"date-time":"2018-05-08T18:55:19Z","timestamp":1525805719000},"page":"733-740","source":"Crossref","is-referenced-by-count":15,"title":["Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks"],"prefix":"10.1109","volume":"38","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9633-2533","authenticated-orcid":false,"given":"Francisco Elias","family":"Rangel-Patino","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2611-5618","authenticated-orcid":false,"given":"Jose Ernesto","family":"Rayas-Sanchez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1175-249X","authenticated-orcid":false,"given":"Andres","family":"Viveros-Wacher","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4115-0999","authenticated-orcid":false,"given":"Jose Luis","family":"Chavez-Hurtado","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Edgar Andrei","family":"Vega-Ochoa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nagib","family":"Hakim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","author":"wu","year":"2000","journal-title":"Experiments Planning Analysis and Parameter Design Optimization"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2014.6818767"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1162\/neco.1992.4.3.415"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2006.885902"},{"key":"ref31","article-title":"Neural space mapping methods for modeling and design of microwave circuits","author":"rayas-s\u00e1nchez","year":"2001"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1016\/0893-6080(89)90020-8"},{"key":"ref37","year":"2016","journal-title":"Serial Advanced Technology Attachment 3 2 Specification"},{"key":"ref36","year":"2016","journal-title":"Peripheral Component Interconnect Express 3 1 Specification"},{"key":"ref35","year":"2016","journal-title":"Universal Serial Bus Revision 3 1 Specification"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/72.557673"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2593902"},{"key":"ref40","first-page":"1","article-title":"Design of discrete-value passive harmonic filters using sequential neural-network approximation and orthogonal array","author":"chang","year":"2005","journal-title":"Proc IEEE PES Transm Distrib Conf Exposit Asia Pac"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.5120\/ijais15-451358"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2014.6818791"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2016.2623902"},{"key":"ref14","first-page":"1","article-title":"Design optimization of full-wave EM models by low-order low-dimension polynomial surrogate functionals","volume":"30","author":"rayas-s\u00e1nchez","year":"2017","journal-title":"Int J Numer Model Electron Netw Dev Fields"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2014.2343192"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691204"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2014.6742899"},{"key":"ref18","first-page":"450","article-title":"Adaptive post-silicon tuning for analog circuits: Concept, analysis and optimization","author":"li","year":"2007","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design (ICCAD)"},{"key":"ref19","author":"bertsekas","year":"2005","journal-title":"Dynamic Programming and Optimal Control"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882518"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/LAMC.2016.7851268"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1007\/978-981-10-6463-0_17"},{"key":"ref3","first-page":"161","article-title":"Design and modeling of a 16-bit 1.5MSPS successive approximation ADC with non-binary capacitor array","author":"miller","year":"2003","journal-title":"Proc Great Lakes Symp VLSI"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2017.2701368"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-49774-5_14"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2504329"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MMM.2015.2514188"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2003.820904"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4.938367"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.112"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCDCS.2017.7959697"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2007.902730"},{"key":"ref22","author":"zhang","year":"2000","journal-title":"Neural Networks for RF and Microwave Design"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1002\/qre.2026"},{"key":"ref24","author":"haykin","year":"1999","journal-title":"Neural Networks A Comprehensive Foundation"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1016\/0041-5553(67)90144-9"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2003.820897"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/EMCSI.2015.7107701"},{"key":"ref25","first-page":"1","article-title":"High-speed interconnect simulation using artificial neural networks","author":"bastola","year":"2015","journal-title":"Proc Intel Design Test Technology Conf"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/8669931\/08355951.pdf?arnumber=8355951","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T20:58:46Z","timestamp":1657745926000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8355951\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,4]]},"references-count":41,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2018.2834403","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,4]]}}}