{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:00:44Z","timestamp":1740132044602,"version":"3.37.3"},"reference-count":25,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["1619415"],"award-info":[{"award-number":["1619415"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2019,7]]},"DOI":"10.1109\/tcad.2018.2846631","type":"journal-article","created":{"date-parts":[[2018,6,12]],"date-time":"2018-06-12T19:19:05Z","timestamp":1528831145000},"page":"1305-1316","source":"Crossref","is-referenced-by-count":4,"title":["Automatic Retiming of Two-Phase Latch-Based Resilient Circuits"],"prefix":"10.1109","volume":"38","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1762-7208","authenticated-orcid":false,"given":"Huimei","family":"Cheng","sequence":"first","affiliation":[]},{"given":"Hsiao-Lun","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Minghe","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Dylan","family":"Hand","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8283-0168","authenticated-orcid":false,"given":"Peter A.","family":"Beerel","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"929","article-title":"Clock skew scheduling for timing speculation","author":"ye","year":"2012","journal-title":"Proc IEEE DATE"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2749462"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2897990"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024760"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2418713"},{"key":"ref15","first-page":"618","article-title":"The case for retiming with explicit reset circuitry","author":"singhal","year":"1997","journal-title":"Proc ICCAD"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062312"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2748001"},{"journal-title":"ISCAS89 International Symposium on Circuits and Systems Sequential Benchmark","year":"0","key":"ref18"},{"journal-title":"Plasma CPU","year":"2014","key":"ref19"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"105","DOI":"10.1109\/JSSC.2015.2464688","article-title":"Carrizo: A high performance, energy efficient 28 nm APU","volume":"51","author":"munger","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref3","first-page":"112","article-title":"Tunable replica circuits and adaptive voltage-frequency techniques for dynamic voltage, temperature, and aging variation tolerance","author":"tschanz","year":"2009","journal-title":"Proc VLSI Circuits"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007145"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457058"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2015.13"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2220912"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2034764"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429512"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007148"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/157485.164998"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/43.541443"},{"article-title":"Retiming synchronous circuitry","year":"1986","author":"leiserson","key":"ref21"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/92.661250"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.1998.655956"},{"journal-title":"Network Flows Theory Algorithms and Applications","year":"1993","author":"ahuja","key":"ref25"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielaam\/43\/8738882\/8382211-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/8738882\/08382211.pdf?arnumber=8382211","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T20:53:51Z","timestamp":1657745631000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8382211\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,7]]},"references-count":25,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2018.2846631","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2019,7]]}}}