{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,24]],"date-time":"2025-10-24T16:43:03Z","timestamp":1761324183120,"version":"3.37.3"},"reference-count":20,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2018,11,1]],"date-time":"2018-11-01T00:00:00Z","timestamp":1541030400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,11,1]],"date-time":"2018-11-01T00:00:00Z","timestamp":1541030400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2018,11,1]],"date-time":"2018-11-01T00:00:00Z","timestamp":1541030400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Research Grants Council of Hong Kong","award":["ECS 25204216","GRF 15204917"],"award-info":[{"award-number":["ECS 25204216","GRF 15204917"]}]},{"DOI":"10.13039\/501100004377","name":"Hong Kong Polytechnic University","doi-asserted-by":"publisher","award":["1-ZVJ2"],"award-info":[{"award-number":["1-ZVJ2"]}],"id":[{"id":"10.13039\/501100004377","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61672140"],"award-info":[{"award-number":["61672140"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2018,11]]},"DOI":"10.1109\/tcad.2018.2857079","type":"journal-article","created":{"date-parts":[[2018,10,16]],"date-time":"2018-10-16T18:46:00Z","timestamp":1539715560000},"page":"2255-2265","source":"Crossref","is-referenced-by-count":5,"title":["Analyzing Data Cache Related Preemption Delay With Multiple Preemptions"],"prefix":"10.1109","volume":"37","author":[{"given":"Wei","family":"Zhang","sequence":"first","affiliation":[{"name":"Department of Computing, The Hong Kong Polytechnic University, Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nan","family":"Guan","sequence":"additional","affiliation":[{"name":"Department of Computing, The Hong Kong Polytechnic University, Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lei","family":"Ju","sequence":"additional","affiliation":[{"name":"School of Software, Shandong University, Jinan, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Weichen","family":"Liu","sequence":"additional","affiliation":[{"name":"School of Computer Science and Engineering, Nanyang Technological University, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/s11241-012-9152-2"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/325478.325479"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/378795.378859"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2002.995708"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2005.12"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2011.27"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2017.35"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2013.6531081"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2006.49"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2014.25"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"700","DOI":"10.1109\/12.689649","article-title":"Analysis of cache-related preemption delay in fixed-priority preemptive scheduling","volume":"47","author":"lee","year":"1998","journal-title":"IEEE Trans Comput"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2584655"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1274858.1274863"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/944696.944698"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA.2005.22"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2038642.2038693"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1347375.1347389"},{"journal-title":"Wcet benchmarks","year":"2008","key":"ref1"},{"key":"ref9","first-page":"182","article-title":"Integrated intra- and inter-task cache analysis for preemptive multi-tasking real-time systems","author":"tan","year":"2004","journal-title":"Proceedings of the International Workshop on Software and Compilers for Embedded Systems"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1017753.1017798"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/8496924\/08493517.pdf?arnumber=8493517","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,8,16]],"date-time":"2023-08-16T17:30:49Z","timestamp":1692207049000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8493517\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,11]]},"references-count":20,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2018.2857079","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2018,11]]}}}