{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T09:59:55Z","timestamp":1740131995296,"version":"3.37.3"},"reference-count":24,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2018,11,1]],"date-time":"2018-11-01T00:00:00Z","timestamp":1541030400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,11,1]],"date-time":"2018-11-01T00:00:00Z","timestamp":1541030400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2018,11,1]],"date-time":"2018-11-01T00:00:00Z","timestamp":1541030400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001459","name":"Ministry of Education - Singapore","doi-asserted-by":"publisher","award":["ARC9\/14"],"award-info":[{"award-number":["ARC9\/14"]}],"id":[{"id":"10.13039\/501100001459","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2018,11]]},"DOI":"10.1109\/tcad.2018.2857081","type":"journal-article","created":{"date-parts":[[2018,7,19]],"date-time":"2018-07-19T18:51:30Z","timestamp":1532026290000},"page":"2720-2731","source":"Crossref","is-referenced-by-count":2,"title":["Predictability and Performance Aware Replacement Policy PVISAM for Unified Shared Caches in Real-time Multicores"],"prefix":"10.1109","volume":"37","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5977-8533","authenticated-orcid":false,"given":"Mohammad Shihabul","family":"Haque","sequence":"first","affiliation":[{"name":"School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9628-3847","authenticated-orcid":false,"given":"Arvind","family":"Easwaran","sequence":"additional","affiliation":[{"name":"School of Computer Science and Engineering, Nanyang Technological University, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2015.84"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1201\/b20200"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830803"},{"key":"ref14","first-page":"9","article-title":"Fair and adaptive online set-based cache partitioning","author":"abousamra","year":"2011","journal-title":"Proc Int Conf Comput Eng Syst"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.073"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/s11241-007-9032-3"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1629435.1629476"},{"article-title":"Caches in WCET analysis–predictability, competitiveness, sensitivity","year":"2008","author":"jan","key":"ref18"},{"journal-title":"Dinero IV Trace-Driven Uniprocessor Cache Simulator","year":"2004","author":"edler","key":"ref19"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1978802.1978814"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/321738.321743"},{"key":"ref6","first-page":"2283","article-title":"Shared data caches conflicts reduction for WCET computation in multi-core architectures","author":"lesage","year":"2010","journal-title":"Proc 20th Int Conf Real-Time Netw Syst"},{"key":"ref5","first-page":"68","article-title":"Using bypass to tighten WCET estimates for multi-core processors with shared instruction caches","author":"hardy","year":"2009","journal-title":"Proc RTSS"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2010.65"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/s11241-012-9160-2"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391545"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2830555"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3062394"},{"article-title":"Benchmarking modern multiprocessors","year":"2011","author":"bienia","key":"ref20"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2013.19"},{"key":"ref21","first-page":"584","article-title":"Controller-aware memory coloring for multicore real-time systems","author":"pan","year":"2018","journal-title":"Proc Symp Appl Comput"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"ref23","first-page":"136","article-title":"The Mälardalen WCET benchmarks: Past, present and future","author":"gustafsson","year":"2010","journal-title":"Proc Int Workshop Worst-Case Execution Time Anal"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/8496924\/08413169.pdf?arnumber=8413169","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,8,16]],"date-time":"2023-08-16T17:30:42Z","timestamp":1692207042000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8413169\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,11]]},"references-count":24,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2018.2857081","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2018,11]]}}}