{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T09:59:54Z","timestamp":1740131994563,"version":"3.37.3"},"reference-count":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2018,11,1]],"date-time":"2018-11-01T00:00:00Z","timestamp":1541030400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,11,1]],"date-time":"2018-11-01T00:00:00Z","timestamp":1541030400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2018,11,1]],"date-time":"2018-11-01T00:00:00Z","timestamp":1541030400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Spanish Ministry of Economy and Competitiveness","award":["TIN2015-65316-P"],"award-info":[{"award-number":["TIN2015-65316-P"]}]},{"name":"HiPEAC Network of Excellence"},{"name":"MINECO and FEDER funds","award":["TIN2014-60404-JIN"],"award-info":[{"award-number":["TIN2014-60404-JIN"]}]},{"name":"MINECO through Ramon y Cajal Post-Doctoral Fellowship","award":["RYC-2013-14717"],"award-info":[{"award-number":["RYC-2013-14717"]}]},{"DOI":"10.13039\/501100000781","name":"European Research Council through EU\u2019s H2020 Research\/Innovation Programme","doi-asserted-by":"publisher","award":["772773"],"award-info":[{"award-number":["772773"]}],"id":[{"id":"10.13039\/501100000781","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2018,11]]},"DOI":"10.1109\/tcad.2018.2857298","type":"journal-article","created":{"date-parts":[[2018,7,18]],"date-time":"2018-07-18T20:08:11Z","timestamp":1531944491000},"page":"2451-2461","source":"Crossref","is-referenced-by-count":2,"title":["EOmesh: Combined Flow Balancing and Deterministic Routing for Reduced WCET Estimates in Embedded Real-Time Systems"],"prefix":"10.1109","volume":"37","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8184-3533","authenticated-orcid":false,"given":"Jordi","family":"Cardona","sequence":"first","affiliation":[{"name":"Departament d&#x2019;Arquitectura de Computadors, Universitat Polit&#x00E8;cnica de Catalunya, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5393-3195","authenticated-orcid":false,"given":"Carles","family":"Hernandez","sequence":"additional","affiliation":[{"name":"Computer Architecture and Operating Systems, Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7951-4028","authenticated-orcid":false,"given":"Jaume","family":"Abella","sequence":"additional","affiliation":[{"name":"Computer Architecture and Operating Systems, Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3344-376X","authenticated-orcid":false,"given":"Francisco J.","family":"Cazorla","sequence":"additional","affiliation":[{"name":"Computer Architecture and Operating Systems, Barcelona Supercomputing Center, Barcelona, Spain"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref33","DOI":"10.1145\/1347375.1347389"},{"doi-asserted-by":"publisher","key":"ref32","DOI":"10.1109\/DASC.2007.4391842"},{"key":"ref31","doi-asserted-by":"crossref","first-page":"583","DOI":"10.1145\/2508148.2485972","article-title":"SurfNoC: A low latency and provably non-interfering approach to secure networks-on-chip","volume":"41","author":"wassel","year":"2013","journal-title":"SIGARCH Comput Archit News"},{"year":"2016","journal-title":"TILE-Gx Processors Family","key":"ref30"},{"key":"ref10","first-page":"330","article-title":"MediaBench: A tool for evaluating and synthesizing multimedia and communications systems","author":"lee","year":"1997","journal-title":"Proc 30th Ann ACM\/IEEE Int l Symp Microarchitecture"},{"year":"2010","journal-title":"FP7 projects","key":"ref11"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/ICVD.2004.1261005"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/ISIE.2008.4677135"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1145\/2656045.2656063"},{"key":"ref15","first-page":"1485","article-title":"Improving performance guarantees in wormhole mesh NoC designs","author":"pani?","year":"2016","journal-title":"Proc DATE"},{"key":"ref16","first-page":"1","article-title":"Modeling high-performance wormhole NoCs for critical real-time embedded systems","author":"pani?","year":"2016","journal-title":"Proc IEEE Real-Time Embedded Technol Appl Symp (RTAS 2003)"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1145\/2401716.2401728"},{"year":"2007","author":"poovey","journal-title":"Characterization of the EEMBC Benchmark Suite","key":"ref18"},{"key":"ref19","first-page":"1090","article-title":"Phase-NoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation","author":"psarras","year":"2015","journal-title":"Proc DATE"},{"year":"2012","journal-title":"SoCLib","key":"ref28"},{"year":"2010","journal-title":"GENeric Embedded SYStem Platform","key":"ref4"},{"doi-asserted-by":"publisher","key":"ref27","DOI":"10.1109\/ECRTS.2009.17"},{"year":"2005","author":"crupnicoff","journal-title":"Deploying quality of service and congestion control in InfiniBand-based data center networks","key":"ref3"},{"year":"2009","key":"ref6"},{"doi-asserted-by":"publisher","key":"ref29","DOI":"10.1109\/ACSD.2012.27"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/MDT.2005.99"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/DSD.2010.30"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/SIES.2013.6601468"},{"year":"2015","journal-title":"ARM Expects Vehicle Compute Performance to Increase 100x in Next Decade","key":"ref2"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1016\/S0743-7315(02)00055-2"},{"year":"2018","journal-title":"NanoC NaNoC design platform","key":"ref1"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1109\/TC.2011.240"},{"year":"2015","author":"rattner","journal-title":"Single-Chip Cloud Computer An Experimental Many-Core Processor from Intel Labs","key":"ref22"},{"key":"ref21","first-page":"537","article-title":"Worst-case communication time analysis of networks-on-chip with shared virtual channels","author":"rambo","year":"2015","journal-title":"Proc DATE"},{"year":"1992","journal-title":"Software Considerations in Airborne Systems and Equipment Certification","key":"ref24"},{"key":"ref23","first-page":"184","article-title":"OpenMP tasking model for Ada: Safety and correctness","author":"royuela","year":"2017","journal-title":"Reliable Software Technologies-Ada-Europe"},{"doi-asserted-by":"publisher","key":"ref26","DOI":"10.1109\/NOCS.2008.4492735"},{"doi-asserted-by":"publisher","key":"ref25","DOI":"10.1109\/NOCS.2012.25"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/8496924\/08412546.pdf?arnumber=8412546","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,8,16]],"date-time":"2023-08-16T17:31:43Z","timestamp":1692207103000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8412546\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,11]]},"references-count":33,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2018.2857298","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2018,11]]}}}