{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,3]],"date-time":"2025-05-03T14:45:08Z","timestamp":1746283508885,"version":"3.37.3"},"reference-count":36,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2018,11,1]],"date-time":"2018-11-01T00:00:00Z","timestamp":1541030400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,11,1]],"date-time":"2018-11-01T00:00:00Z","timestamp":1541030400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2018,11,1]],"date-time":"2018-11-01T00:00:00Z","timestamp":1541030400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2018,11]]},"DOI":"10.1109\/tcad.2018.2857318","type":"journal-article","created":{"date-parts":[[2018,10,16]],"date-time":"2018-10-16T18:46:00Z","timestamp":1539715560000},"page":"2485-2496","source":"Crossref","is-referenced-by-count":3,"title":["Formal Modeling and Verification of Controllers for a Family of DRAM Caches"],"prefix":"10.1109","volume":"37","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1438-0617","authenticated-orcid":false,"given":"Debiprasanna","family":"Sahoo","sequence":"first","affiliation":[{"name":"School of Electrical Sciences, Indian Institute of Technology Bhubaneswar, Bhubaneswar, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2886-791X","authenticated-orcid":false,"given":"Swaraj","family":"Sha","sequence":"additional","affiliation":[{"name":"School of Electrical Sciences, Indian Institute of Technology Bhubaneswar, Bhubaneswar, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Manoranjan","family":"Satpathy","sequence":"additional","affiliation":[{"name":"School of Electrical Sciences, Indian Institute of Technology Bhubaneswar, Bhubaneswar, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1638-4195","authenticated-orcid":false,"given":"Madhu","family":"Mutyam","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering, Indian Institute of Technology Madras, Chennai, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Ramesh","sequence":"additional","affiliation":[{"name":"ECS Lab, General Motors Research and Development, Warren, MI, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Partha","family":"Roop","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Auckland, Auckland, New Zealand"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"article-title":"High bandwidth memory interface","year":"2003","author":"gillingham","key":"ref33"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2414456"},{"article-title":"The SAL language manual","year":"2003","author":"de moura","key":"ref31"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2016.88"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"journal-title":"Software Product-Line Engineering A Family-Based Software Development Process","year":"1999","author":"weiss","key":"ref35"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2011.7477494"},{"key":"ref10","doi-asserted-by":"crossref","first-page":"887","DOI":"10.1109\/SC.2016.75","article-title":"DCA: A DRAM-cache-aware DRAM controller","author":"huang","year":"2016","journal-title":"Proc SC16 Int Conf High Perform Comput Netw Stor Anal"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2015.2461155"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155673"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056027"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2015.34"},{"journal-title":"Memory Systems&#x2014;Cache DRAM Disk","year":"2007","author":"jacob","key":"ref15"},{"key":"ref16","first-page":"1050","article-title":"MCXplore: Automating the validation process of dram memory controller designs","volume":"37","author":"hassan","year":"2018","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339668"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2016.2526003"},{"journal-title":"DDR3 SDRAM Part MT41J256M8","year":"2006","key":"ref19"},{"article-title":"Formal methods for functional verification of cache-coherent system-on-chip","year":"2015","author":"kriouile","key":"ref28"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2628071.2628089"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2001.922002"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/54.922799"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.36"},{"key":"ref29","article-title":"Revisiting the complexity of hardware cache coherence and some implications","volume":"11","author":"komuravelli","year":"2014","journal-title":"Trans Archit Compiler Optim"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601880"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.30"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485957"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.2007462"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.51"},{"article-title":"Hitting the memory wall: Implications of the obvious","year":"1994","author":"wulf","key":"ref1"},{"journal-title":"JESD79-4 DDR4 SDRAM","year":"2012","key":"ref20"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750387"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/CASES.2013.6662515"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2018.8297308"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835963"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/248621.248624"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/71.406955"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/8496924\/08493587.pdf?arnumber=8493587","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,8,16]],"date-time":"2023-08-16T17:30:19Z","timestamp":1692207019000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8493587\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,11]]},"references-count":36,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2018.2857318","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2018,11]]}}}