{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,4]],"date-time":"2025-11-04T10:39:56Z","timestamp":1762252796159,"version":"3.37.3"},"reference-count":51,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001659","name":"Deutsche Forschungsgemeinschaft","doi-asserted-by":"publisher","award":["WU 245\/19-1","HE1686\/4-1 (FAST)"],"award-info":[{"award-number":["WU 245\/19-1","HE1686\/4-1 (FAST)"]}],"id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2019,10]]},"DOI":"10.1109\/tcad.2018.2864255","type":"journal-article","created":{"date-parts":[[2018,8,7]],"date-time":"2018-08-07T19:09:11Z","timestamp":1533668951000},"page":"1956-1968","source":"Crossref","is-referenced-by-count":12,"title":["Built-In Test for Hidden Delay Faults"],"prefix":"10.1109","volume":"38","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6691-6802","authenticated-orcid":false,"given":"Matthias","family":"Kampmann","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1228-3402","authenticated-orcid":false,"given":"Michael A.","family":"Kochte","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3099-7385","authenticated-orcid":false,"given":"Chang","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2296-1956","authenticated-orcid":false,"given":"Eric","family":"Schneider","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3717-3939","authenticated-orcid":false,"given":"Sybille","family":"Hellebrand","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4536-8290","authenticated-orcid":false,"given":"Hans-Joachim","family":"Wunderlich","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1386979"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2010.5469617"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2035550"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2007.4437575"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2007.4437576"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.863742"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2009.43"},{"key":"ref36","first-page":"200","article-title":"Self-testing of multichip logic modules","author":"bardell","year":"1982","journal-title":"Proc IEEE Int Test Conf (ITC)"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2015.26"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2014.7035360"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1270904"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271094"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2005.1584076"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2012.6401581"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2011.2135354"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894202"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373350"},{"journal-title":"Easily Implement Pll Clock Swithching for At-Speed Test","year":"2006","author":"press","key":"ref21"},{"key":"ref24","first-page":"1353","article-title":"An on-chip clock generation scheme for faster-than-at-speed delay testing","author":"pei","year":"2010","journal-title":"Proc Design and Test in Europe (DATE)"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700564"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041774"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2015.7059058"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/43.833205"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/54.867894"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2043591"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2043570"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2008.42"},{"key":"ref12","first-page":"1291","article-title":"As-robust-as-possible test generation in the presence of small delay defects using pseudo-Boolean optimization","author":"eggersgl\u00fc\u00df","year":"2011","journal-title":"Proceedings of the Design Automation and Test in Europe (DATE)"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2013.6651925"},{"key":"ref14","first-page":"105","article-title":"Experiments at detecting delay faults using multiple higher frequency clocks and results from neighboring die","author":"yan","year":"2003","journal-title":"Proc IEEE Int Test Conf (ITC)"},{"key":"ref15","first-page":"1","article-title":"Defining faster-than-at-speed delay tests","volume":"2","author":"amodeo","year":"2005","journal-title":"Cadence Nanometer Test Quarterly eNewsletter"},{"key":"ref16","first-page":"198","article-title":"A novel framework for faster-than-at-speed delay test considering IR-drop effects","author":"ahmed","year":"2006","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design (ICCAD)"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700561"},{"key":"ref18","first-page":"1","article-title":"Silicon evaluation of longest path avoidance testing for small delay defects","author":"turakhia","year":"2007","journal-title":"Proc IEEE Int Test Conf (ITC)"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2012.6231084"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2014.6818780"},{"key":"ref3","first-page":"1","article-title":"Non-intrusive integration of advanced diagnosis features in automotive E\/E-architectures","author":"abelein","year":"2014","journal-title":"Proc Design Autom Test Eur Conf Exhibition (DATE)"},{"key":"ref6","article-title":"Online LBIST for automotive on a multicore processor","author":"mclaurin","year":"2017","journal-title":"Proc 1st IEEE Int Workshop Autom Rel Test (ART)"},{"key":"ref5","article-title":"From manufacturing to functional safety use, how infield built-in self-test architecture must evolve to support real time system constraints","author":"eychenne","year":"2017","journal-title":"Proc 1st IEEE Int Workshop Autom Rel Test (ART)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-8297-1"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2010.5560326"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.0077"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2006.261012"},{"journal-title":"Computers and Intractability&#x2014;A Guide to the Theory of NP-completeness","year":"1979","author":"garey","key":"ref46"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4684-2001-2_9"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/CSO.2010.240"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/1542362.1542368"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2099243"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.826558"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2011.6139131"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1386955"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/8844133\/08428460.pdf?arnumber=8428460","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T20:57:28Z","timestamp":1657745848000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8428460\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,10]]},"references-count":51,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2018.2864255","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2019,10]]}}}