{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:56:03Z","timestamp":1759146963379,"version":"3.37.3"},"reference-count":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Xilinx, Inc."}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2019,11]]},"DOI":"10.1109\/tcad.2018.2877017","type":"journal-article","created":{"date-parts":[[2018,10,19]],"date-time":"2018-10-19T18:45:48Z","timestamp":1539974748000},"page":"2113-2126","source":"Crossref","is-referenced-by-count":25,"title":["A New Paradigm for FPGA Placement Without Explicit Packing"],"prefix":"10.1109","volume":"38","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9887-5109","authenticated-orcid":false,"given":"Wuxi","family":"Li","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5705-2501","authenticated-orcid":false,"given":"David Z.","family":"Pan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923063"},{"journal-title":"Xilinx Vivado Design Suite","year":"2018","key":"ref32"},{"journal-title":"OpenMP 4 0","year":"2018","key":"ref31"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/3174849"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2007.4380635"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062279"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2729349"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203821"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2778058"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203880"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2980085"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2872334.2886419"},{"journal-title":"Xilinx Virtex UltraScale Product Table","year":"2018","key":"ref18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.846365"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.2307\/2312726"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/370155.370567"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1807167.1807184"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296426"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/RECONFIG.2005.23"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/3036669.3038241"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/605440.605448"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024908"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1155\/2010\/158602"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1997.606687"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2012.6412103"},{"key":"ref1","first-page":"213","article-title":"VPR: A new packing, placement and routing tool for FPGA research","author":"betz","year":"1997","journal-title":"Proc FPL"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.925783"},{"key":"ref22","first-page":"747","article-title":"ComPLx: A competitive primal-dual lagrange optimization for global placement","author":"kim","year":"2012","journal-title":"Proc DAC"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691143"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2170567"},{"key":"ref23","first-page":"922","article-title":"UTPlaceF 3.0: A parallelization framework for modern FPGA global placement","author":"li","year":"2017","journal-title":"Proc ICCAD"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429539"},{"article-title":"Method and system for high speed detailed placement of cells within an integrated circuit design","year":"2002","author":"hill","key":"ref25"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/8877482\/08500228.pdf?arnumber=8500228","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T21:08:51Z","timestamp":1657746531000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8500228\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,11]]},"references-count":33,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2018.2877017","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2019,11]]}}}