{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,10]],"date-time":"2026-01-10T08:10:36Z","timestamp":1768032636527,"version":"3.49.0"},"reference-count":43,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61401008"],"award-info":[{"award-number":["61401008"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61704005"],"award-info":[{"award-number":["61704005"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61571023"],"award-info":[{"award-number":["61571023"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004826","name":"Natural Science Foundation of Beijing Municipality","doi-asserted-by":"publisher","award":["4192035"],"award-info":[{"award-number":["4192035"]}],"id":[{"id":"10.13039\/501100004826","id-type":"DOI","asserted-by":"publisher"}]},{"name":"International Collaboration Project","award":["B16001"],"award-info":[{"award-number":["B16001"]}]},{"name":"National Key Technology Program of China","award":["2017ZX01032101"],"award-info":[{"award-number":["2017ZX01032101"]}]},{"DOI":"10.13039\/501100009592","name":"Beijing Municipal Science and Technology Commission","doi-asserted-by":"publisher","award":["Z161100000216149"],"award-info":[{"award-number":["Z161100000216149"]}],"id":[{"id":"10.13039\/501100009592","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100002367","name":"Chinese Academy of Sciences","doi-asserted-by":"publisher","award":["CARCH201602"],"award-info":[{"award-number":["CARCH201602"]}],"id":[{"id":"10.13039\/501100002367","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2020,4]]},"DOI":"10.1109\/tcad.2019.2897707","type":"journal-article","created":{"date-parts":[[2019,2,5]],"date-time":"2019-02-05T19:54:20Z","timestamp":1549396460000},"page":"803-815","source":"Crossref","is-referenced-by-count":8,"title":["A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration"],"prefix":"10.1109","volume":"39","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9972-0478","authenticated-orcid":false,"given":"Bi","family":"Wu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pengcheng","family":"Dai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2477-314X","authenticated-orcid":false,"given":"Yuanqing","family":"Cheng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5172-4736","authenticated-orcid":false,"given":"Ying","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8424-7040","authenticated-orcid":false,"given":"Jianlei","family":"Yang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2999-7903","authenticated-orcid":false,"given":"Zhaohao","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dijun","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8088-0404","authenticated-orcid":false,"given":"Weisheng","family":"Zhao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","first-page":"329","article-title":"Multi retention level STT-RAM cache designs with a dynamic refresh scheme","author":"sun","year":"2017","journal-title":"Proc IEEE\/ACM Inter Symp Microarch (MICRO'06)"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2449739"},{"key":"ref33","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4939-2581-0","author":"jha","year":"2015","journal-title":"Thermal Sensors Principles and Applications for Semiconductor Industries"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283826"},{"key":"ref30","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2024716.2024718","article-title":"The gem5 simulator","volume":"39","author":"binkert","year":"2011","journal-title":"ACM SIGARCH Comput Archit News"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555779"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2288692"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.21"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2897979"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2483028.2483060"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2014.6783387"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687448"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2351581"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISPAW.2011.25"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2644279"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2014.07.019"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1038\/s41467-018-03140-z"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/43.39068"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1063\/1.4820457"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424242"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333709"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2729404"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2247656"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.33"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2424440"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681639"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605420"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865703"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1147\/rd.524.0465"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2016.25"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-018-0160-7"},{"key":"ref1","first-page":"87","article-title":"Era of multi-core processors","volume":"2","author":"jagtap","year":"2009","journal-title":"Power"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2016.2608910"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.876103"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-012-0859-6"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2017.103"},{"key":"ref24","first-page":"108","article-title":"A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS","author":"howard","year":"2010","journal-title":"Proc IEEE Int Solid-State Circuits Conf (ISSCC)"},{"key":"ref41","first-page":"1","article-title":"Asynchronous asymmetrical write termination (AAWT) for a low power STT-MRAM","author":"bishnoi","year":"2014","journal-title":"Proc Design and Test in Europe (DATE) Conf"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2014.2376112"},{"key":"ref26","first-page":"365","article-title":"Dark silicon and the end of multicore scaling","author":"esmaeilzadeh","year":"2011","journal-title":"2011 38th Annual International Symposium on Computer Architecture (ISCA) ISCA"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2018.00068"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736043"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9042369\/08634911.pdf?arnumber=8634911","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,13]],"date-time":"2023-09-13T11:59:34Z","timestamp":1694606374000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8634911\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,4]]},"references-count":43,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2019.2897707","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,4]]}}}