{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,11]],"date-time":"2026-06-11T16:13:30Z","timestamp":1781194410414,"version":"3.54.1"},"reference-count":28,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61420106004"],"award-info":[{"award-number":["61420106004"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61732013"],"award-info":[{"award-number":["61732013"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61751207"],"award-info":[{"award-number":["61751207"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2020,4]]},"DOI":"10.1109\/tcad.2019.2901243","type":"journal-article","created":{"date-parts":[[2019,2,22]],"date-time":"2019-02-22T20:00:27Z","timestamp":1550865627000},"page":"830-842","source":"Crossref","is-referenced-by-count":25,"title":["ParRA: A Shared Memory Parallel FPGA Router Using Hybrid Partitioning Approach"],"prefix":"10.1109","volume":"39","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4783-446X","authenticated-orcid":false,"given":"Dekui","family":"Wang","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3119-3242","authenticated-orcid":false,"given":"Zhenhua","family":"Duan","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Cong","family":"Tian","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Bohu","family":"Huang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Nan","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174246"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577299"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2768416"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2617593"},{"key":"ref14","volume":"497","author":"betz","year":"2012","journal-title":"Architecture and CAD for Deep-Submicron FPGAs"},{"key":"ref15","first-page":"156","article-title":"Computing the shortest path: A search meets graph theory","author":"goldberg","year":"2005","journal-title":"16th Ann ACM-SIAM Symp on Discrete Algorithms"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2007.4405687"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382691"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"213","DOI":"10.1007\/3-540-63465-7_226","article-title":"VPR: A new packing, placement and routing tool for FPGA research","author":"betz","year":"1997","journal-title":"Field-Programmable Logic and Applications"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275134"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021732"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593177"},{"key":"ref27","article-title":"Parallel FPGA router using sub-gradient method and Steiner tree","author":"agrawal","year":"2018","journal-title":"arXiv preprint arXiv 1803 03885"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2165715"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2017.34"},{"key":"ref5","first-page":"1","article-title":"ParaLaR: A parallel FPGA router based on Lagrangian relaxation","author":"hoo","year":"2015","journal-title":"Proc Int Conf Field Program Logic Appl"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203829"},{"key":"ref7","first-page":"1","article-title":"Parallel FPGA routing: Survey and challenges","author":"stojilovi?","year":"2017","journal-title":"Proc Int Conf Field Program Logic Appl"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-46117-5_28"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372558"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"111","DOI":"10.1109\/FPGA.1995.242049","article-title":"pathfinder: a negotiation-based performance-driven router for fpgas","author":"mcmurchie","year":"1995","journal-title":"Third International ACM Symposium on Field-Programmable Gate Arrays"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2011.84"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2629579"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/581199.581224"},{"key":"ref24","author":"mishchenko","year":"2007","journal-title":"ABC A System for Sequential Synthesis and Verification"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2017.45"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2010.5681758"},{"key":"ref25","year":"2018","journal-title":"Parrat32"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9042369\/08649665.pdf?arnumber=8649665","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:02:53Z","timestamp":1651068173000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8649665\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,4]]},"references-count":28,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2019.2901243","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,4]]}}}