{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,13]],"date-time":"2026-06-13T20:01:09Z","timestamp":1781380869424,"version":"3.54.1"},"reference-count":43,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["2014-TJ-2528"],"award-info":[{"award-number":["2014-TJ-2528"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2020,4]]},"DOI":"10.1109\/tcad.2019.2907909","type":"journal-article","created":{"date-parts":[[2019,3,27]],"date-time":"2019-03-27T21:50:11Z","timestamp":1553723411000},"page":"922-935","source":"Crossref","is-referenced-by-count":24,"title":["Enhancing Network-on-Chip Performance by Reusing Trace Buffers"],"prefix":"10.1109","volume":"39","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8398-476X","authenticated-orcid":false,"given":"Neetu","family":"Jindal","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shubhani","family":"Gupta","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Divya Praneetha","family":"Ravipati","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2508-7531","authenticated-orcid":false,"given":"Preeti Ranjan","family":"Panda","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1657-8523","authenticated-orcid":false,"given":"Smruti R.","family":"Sarangi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2827928"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927052"},{"key":"ref33","author":"jafri","year":"2013","journal-title":"apSLIP A High-performance Adaptive-Effort Pipelined Switch Allocator"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/INFCOM.1992.263574"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00049"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2000.876165"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898020"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2010.27"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/AINA.2014.144"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/HOTI.2016.023"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/40.566196"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555781"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2593902"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2658564"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090658"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IES.2006.357464"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2004.1431260"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2009.5413157"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2015.03.003"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2012.6231078"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429506"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/NAS.2012.39"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2002.1016885"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.50"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/71.127260"},{"key":"ref6","first-page":"354","article-title":"Application-specific buffer space allocation for networks-on-chip router design","author":"hu","year":"2004","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design (ICCAD)"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2268548"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378783"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2002.1012681"},{"key":"ref7","first-page":"105","article-title":"Power-driven design of router microarchitectures in on-chip networks","author":"wang","year":"2003","journal-title":"Proc 36th Annu IEEE\/ACM Int Symp Microarchit"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416640"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364402"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VDAT.2009.5158125"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.3850\/9783981537079_0400"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2005.427"},{"key":"ref21","first-page":"127","article-title":"DiAMOND: Distributed alteration of messages for on-chip network debug","author":"abdel-khalek","year":"2014","journal-title":"Proc NOCS"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665691"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2014.7008756"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557149"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.169"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2016.17"},{"key":"ref43","article-title":"Efficient microarchitecture for network-on-chip routers","author":"becker","year":"2012"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/3079079.3079090"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9042369\/08675353.pdf?arnumber=8675353","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:02:52Z","timestamp":1651068172000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8675353\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,4]]},"references-count":43,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2019.2907909","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,4]]}}}