{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T16:34:22Z","timestamp":1773246862151,"version":"3.50.1"},"reference-count":38,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2020,7,1]],"date-time":"2020-07-01T00:00:00Z","timestamp":1593561600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,7,1]],"date-time":"2020-07-01T00:00:00Z","timestamp":1593561600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,7,1]],"date-time":"2020-07-01T00:00:00Z","timestamp":1593561600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100007053","name":"Mentor Graphics Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100007053","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2020,7]]},"DOI":"10.1109\/tcad.2019.2915324","type":"journal-article","created":{"date-parts":[[2019,5,8]],"date-time":"2019-05-08T00:50:05Z","timestamp":1557276605000},"page":"1456-1469","source":"Crossref","is-referenced-by-count":22,"title":["Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations"],"prefix":"10.1109","volume":"39","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4759-8663","authenticated-orcid":false,"given":"Ankur","family":"Sharma","sequence":"first","affiliation":[]},{"given":"David","family":"Chinnery","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3730-0213","authenticated-orcid":false,"given":"Tiago","family":"Reimann","sequence":"additional","affiliation":[]},{"given":"Sarvesh","family":"Bhardwaj","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6073-1719","authenticated-orcid":false,"given":"Chris","family":"Chu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/99.660313"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/2872334.2872358"},{"key":"ref32","first-page":"43","article-title":"Calculating the effective capacitance for the RC interconnect in VDSM technologies","author":"abbaspour","year":"2003","journal-title":"Proc Asia South Pacific Design Automat Conf"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.1999.745217"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/43.331409"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/217474.217556"},{"key":"ref36","author":"bakoglu","year":"1990","journal-title":"Circuits Interconnections and Packaging for VLSI"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/SLIP.2013.6681682"},{"key":"ref34","article-title":"Method of designing a digital circuit by correlating different static timing analyzers","author":"moon","year":"2010"},{"key":"ref10","first-page":"149","article-title":"Linear programming for sizing, \n$V_{\\mathrm{ th}}$\n and \n$V_{\\mathrm{ dd}}$\n assignment","author":"chinnery","year":"2005","journal-title":"Proc ACM Int Symp Low Power Electron Design"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/43.851993"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.895793"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278690"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/43.771182"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2247657"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/43.298040"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2035575"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1970353.1970357"},{"key":"ref19","first-page":"395","article-title":"Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step","author":"tennakoon","year":"2002","journal-title":"Proc ACM Int Conf Comput -Aided Design"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/640000.640009"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372601"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/332357.332377"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2451916.2451959"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-0292-0_23"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1063\/1.1697872"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203797"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691156"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429428"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2160916.2160950"},{"key":"ref9","first-page":"158","article-title":"Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization","author":"nguyen","year":"2003","journal-title":"Proc ACM Int Symp Low Power Electron Design"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2305847"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1960397.1960436"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105409"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2018872"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2013.6572398"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429427"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2801231"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2647956"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9119884\/08708206.pdf?arnumber=8708206","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:03:24Z","timestamp":1651068204000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8708206\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,7]]},"references-count":38,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2019.2915324","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,7]]}}}