{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:48:07Z","timestamp":1759146487779,"version":"3.37.3"},"reference-count":51,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"NSF, China","doi-asserted-by":"publisher","award":["61871242","61571248"],"award-info":[{"award-number":["61871242","61571248"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Zhejiang Provincial NSF","award":["Y19F040013"],"award-info":[{"award-number":["Y19F040013"]}]},{"DOI":"10.13039\/501100004387","name":"K. C. Wong Magna Fund in Ningbo University","doi-asserted-by":"publisher","award":["H2020-ERC-2014-ADG 669354 CyberCare"],"award-info":[{"award-number":["H2020-ERC-2014-ADG 669354 CyberCare"]}],"id":[{"id":"10.13039\/501100004387","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001711","name":"Swiss National Science Foundation","doi-asserted-by":"publisher","award":["200021-169084 MAJesty"],"award-info":[{"award-number":["200021-169084 MAJesty"]}],"id":[{"id":"10.13039\/501100001711","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2020,8]]},"DOI":"10.1109\/tcad.2019.2925392","type":"journal-article","created":{"date-parts":[[2019,6,27]],"date-time":"2019-06-27T20:07:46Z","timestamp":1561666066000},"page":"1621-1634","source":"Crossref","is-referenced-by-count":19,"title":["Advanced Functional Decomposition Using Majority and Its Applications"],"prefix":"10.1109","volume":"39","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5718-4822","authenticated-orcid":false,"given":"Zhufei","family":"Chu","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0229-8766","authenticated-orcid":false,"given":"Mathias","family":"Soeken","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3831-3876","authenticated-orcid":false,"given":"Yinshui","family":"Xia","sequence":"additional","affiliation":[]},{"given":"Lunyao","family":"Wang","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7827-3215","authenticated-orcid":false,"given":"Giovanni","family":"De Micheli","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1965.264064"},{"key":"ref38","doi-asserted-by":"crossref","first-page":"1447","DOI":"10.1109\/PROC.1976.10351","article-title":"on multiple fault analysis in combinational circuits by means of boolean difference","volume":"64","author":"das","year":"1976","journal-title":"Proceedings of the IEEE"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2015.7357181"},{"key":"ref32","first-page":"1","article-title":"Faster logic manipulation for large designs","author":"mishchenko","year":"2013","journal-title":"Proc IWLS"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/288548.288586"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.1013899"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-49052-6_1"},{"key":"ref36","first-page":"687","article-title":"Resynthesis of multi-level circuits under tight constraints using symbolic optimization","author":"kravets","year":"2002","journal-title":"Proc ICCAD"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/FOCS.1962.16"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1964.263903"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887925"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2007.4397290"},{"key":"ref29","first-page":"1","article-title":"Decision diagrams and pass transistor logic synthesis","author":"bertacco","year":"1997","journal-title":"Proc IWLS"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2015.2460377"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1038\/530144a"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2018.8297400"},{"key":"ref22","first-page":"74","volume":"29","author":"ashenhurst","year":"1959","journal-title":"The Decomposition of Switching Functions"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1997.643371"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1137\/0111022"},{"journal-title":"A New Approach to the Design of Switching Circuits","year":"1962","author":"curtis","key":"ref23"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681549"},{"key":"ref25","first-page":"1","article-title":"Enumeration of irredundant circuit structures","author":"mishchenko","year":"2014","journal-title":"Proc IWLS"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021735"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevA.71.022316"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147048"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2488484"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_5"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2017.7858312"},{"article-title":"Optimal combinational multi-level logic synthesis","year":"2009","author":"ernst","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2011.6081434"},{"key":"ref15","first-page":"1","article-title":"LUT mapping and optimization for majority-inverter graphs","author":"haaswijk","year":"2016","journal-title":"Proc IWLS"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.3850\/9783981537079_0281"},{"key":"ref17","first-page":"830","article-title":"Busy man’s synthesis: Combinational delay optimization with SAT","author":"soeken","year":"2017","journal-title":"Proc DATE"},{"key":"ref18","article-title":"SAT based exact synthesis using DAG topology families","author":"haaswijk","year":"2018","journal-title":"Proc DAC"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/343647.343734"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1126\/science.284.5412.289"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488792"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1126\/science.1120506"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1063\/1.2834714"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1996.545580"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927035"},{"article-title":"An approach to disjoint-support decomposition of logic functions","year":"2001","author":"mishchenko","key":"ref49"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593158"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.2017.44"},{"key":"ref45","first-page":"747","article-title":"Some theorems useful in threshold logic for enumerating Boolean functions","author":"goto","year":"1962","journal-title":"Proc Int Fed Inf Process Congr"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1978.1675103"},{"journal-title":"Synthesis and Optimization of Digital Circuits New Delhi","year":"1994","author":"micheli","key":"ref47"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-02777-2_5"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2664059"},{"journal-title":"The Art of Computer Programming Volume 4 Fascicle 6 Satisfiability","year":"2015","author":"knuth","key":"ref44"},{"key":"ref43","article-title":"Practical SAT—A tutorial on applied satisfiability solving","author":"e\u00e9n","year":"2007","journal-title":"Proc Formal Methods in Computer Aided Design (FMCAD)"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9142465\/08747480.pdf?arnumber=8747480","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:07:08Z","timestamp":1651068428000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8747480\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,8]]},"references-count":51,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2019.2925392","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2020,8]]}}}