{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T16:05:22Z","timestamp":1780675522266,"version":"3.54.1"},"reference-count":21,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100014188","name":"Ministry of Science and ICT, South Korea","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100014188","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Information Technology Research Center Support Program"},{"DOI":"10.13039\/501100010418","name":"Institute for Information and Communications Technology Promotion","doi-asserted-by":"publisher","award":["IITP-2019-2016-0-00309-002"],"award-info":[{"award-number":["IITP-2019-2016-0-00309-002"]}],"id":[{"id":"10.13039\/501100010418","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2020,8]]},"DOI":"10.1109\/tcad.2019.2926484","type":"journal-article","created":{"date-parts":[[2019,7,7]],"date-time":"2019-07-07T19:19:04Z","timestamp":1562527144000},"page":"1744-1749","source":"Crossref","is-referenced-by-count":8,"title":["Compact Topology-Aware Bus Routing for Design Regularity"],"prefix":"10.1109","volume":"39","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5879-8313","authenticated-orcid":false,"given":"Daeyeon","family":"Kim","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0170-1354","authenticated-orcid":false,"given":"Sanggi","family":"Do","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4141-6411","authenticated-orcid":false,"given":"Sung-Yun","family":"Lee","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3015-1806","authenticated-orcid":false,"given":"Seokhyeong","family":"Kang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","first-page":"2130","DOI":"10.1109\/TCAD.2007.907003","article-title":"BoxRouter: A new global router based on box expansion and progressive ILP","volume":"26","author":"cho","year":"2007","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2006082"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923255"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907068"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/43.144853"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/201310.201328"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1984.1585880"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1231996.1232025"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2834424"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TSSC.1968.300136"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2102780"},{"key":"ref3","author":"liao","year":"2018","journal-title":"ICCAD 2018 CAD Contest Obstacle-Aware On-Track Bus Routing"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2013991"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"709","DOI":"10.1109\/TCAD.2012.2235124","article-title":"NCTU-GR 2.0: Multithreaded collision-aware global routing with bounded-length maze routing","volume":"32","author":"liu","year":"2013","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref8","first-page":"576","article-title":"FastRoute 4.0: Global router with efficient via minimization","author":"xu","year":"2009","journal-title":"Proc ASPDAC"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2066030"},{"key":"ref2","article-title":"Routing algorithms for high-performance VLSI packaging","author":"ozdal","year":"2005"},{"key":"ref1","article-title":"Layout regularity for design and manufacturability","author":"sole","year":"2012"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.917590"},{"key":"ref20","year":"2017","journal-title":"Boost Geometry Library"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/602259.602266"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9142465\/08755281.pdf?arnumber=8755281","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:07:08Z","timestamp":1651068428000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8755281\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,8]]},"references-count":21,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2019.2926484","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,8]]}}}