{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,23]],"date-time":"2026-04-23T14:44:50Z","timestamp":1776955490357,"version":"3.51.4"},"reference-count":56,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2020,9,1]],"date-time":"2020-09-01T00:00:00Z","timestamp":1598918400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,9,1]],"date-time":"2020-09-01T00:00:00Z","timestamp":1598918400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,9,1]],"date-time":"2020-09-01T00:00:00Z","timestamp":1598918400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100002418","name":"Intel Corporation","doi-asserted-by":"publisher","award":["INTEL11EG01"],"award-info":[{"award-number":["INTEL11EG01"]}],"id":[{"id":"10.13039\/100002418","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2020,9]]},"DOI":"10.1109\/tcad.2019.2926495","type":"journal-article","created":{"date-parts":[[2019,7,7]],"date-time":"2019-07-07T19:19:04Z","timestamp":1562527144000},"page":"1820-1833","source":"Crossref","is-referenced-by-count":20,"title":["CAMON: Low-Cost Silicon Photonic Chiplet for Manycore Processors"],"prefix":"10.1109","volume":"39","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7139-724X","authenticated-orcid":false,"given":"Zhehui","family":"Wang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhifei","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9089-7752","authenticated-orcid":false,"given":"Jiang","family":"Xu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9747-2586","authenticated-orcid":false,"given":"Yi-Shing","family":"Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2313-7144","authenticated-orcid":false,"given":"Jun","family":"Feng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0276-1199","authenticated-orcid":false,"given":"Xuanqi","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7282-0495","authenticated-orcid":false,"given":"Shixi","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jiaxu","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2018.8512157"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.17"},{"key":"ref33","doi-asserted-by":"crossref","first-page":"477","DOI":"10.1145\/1854273.1854332","article-title":"ATAC: A 1000-core cache-coherent processor with on-chip optical network","author":"kurian","year":"2010","journal-title":"Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques (PACT)"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/1995896.1995941"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2017.11.015"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2009.51"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/3140659.3080231"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00066"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2017.109"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/3154840"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000115"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2013.26"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815978"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2445825"},{"key":"ref1","year":"2015","journal-title":"International Technology Roadmap for Semiconductors"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2012.103"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540728"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2320510"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2597652.2597664"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/HOTI.2017.18"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2008.4751906"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815977"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"ref51","year":"2017","journal-title":"TN-40&#x2013;07 Calculating Memory System Power for DDR4 SDRAM"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1145\/1736065.1736069"},{"key":"ref55","year":"2014","journal-title":"Single-Mode Fiber Optics"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/JLT.2010.2101580"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1038\/nature03569"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/JSTQE.2014.2300184"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2009.5071460"},{"key":"ref11","first-page":"1","article-title":"Optical ring network-on-chip (ORNoC): Architecture and design methodology","author":"beux","year":"2011","journal-title":"Proc Design Autom Test Eur Conf Exhibition (DATE)"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919636"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1999946.1999960"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2014.7008765"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2967614"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630060"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2567940"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.23"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.323"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446075"},{"key":"ref4","first-page":"1","article-title":"22.5 A $4\\times20$\nGb\/s WDM ring-based hybrid CMOS silicon photonics transceiver","author":"rakowski","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref3","first-page":"1305","article-title":"125-$\\mu\\text{m}$\n-pitch $\\times12$\n-channel &#x2018;optical pin&#x2019; array as I\/O structure for novel miniaturized optical transceiver chips","author":"uemura","year":"2015","journal-title":"Proc IEEE 65th Electron Compon Technol Conf (ECTC)"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.35"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2014298"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555809"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416626"},{"key":"ref49","doi-asserted-by":"crossref","first-page":"92","DOI":"10.1145\/1105734.1105747","article-title":"Multifacet&#x2019;s general execution-driven multiprocessor simulator (GEMS) toolset","volume":"33","author":"martin","year":"2005","journal-title":"ACM SIGARCH Comput Archit News"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.78"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.891495"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2017.7858410"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1145\/2857058.2857066"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310208"},{"key":"ref42","year":"2014","journal-title":"Hybrid memory cube specification 2 0"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/66.843637"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669166"},{"key":"ref43","year":"2019","journal-title":"Benchmark Distribution and Benchmark Run Rules"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9171928\/08755274.pdf?arnumber=8755274","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:06:50Z","timestamp":1651068410000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8755274\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9]]},"references-count":56,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2019.2926495","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,9]]}}}