{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,31]],"date-time":"2025-12-31T12:19:41Z","timestamp":1767183581263,"version":"3.37.3"},"reference-count":40,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["1018621"],"award-info":[{"award-number":["1018621"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2020,10]]},"DOI":"10.1109\/tcad.2019.2940680","type":"journal-article","created":{"date-parts":[[2019,9,11]],"date-time":"2019-09-11T19:54:46Z","timestamp":1568231686000},"page":"2503-2515","source":"Crossref","is-referenced-by-count":17,"title":["Logic Synthesis of Approximate Circuits"],"prefix":"10.1109","volume":"39","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0470-6364","authenticated-orcid":false,"given":"Swagath","family":"Venkataramani","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vivek J.","family":"Kozhikkottu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amit","family":"Sabne","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0735-9695","authenticated-orcid":false,"given":"Kaushik","family":"Roy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anand","family":"Raghunathan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/1754405.1754411"},{"key":"ref38","first-page":"297","article-title":"The use of observability and external don’t cares for the simplification of multi-level networks","author":"savoj","year":"1990","journal-title":"Proc DAC"},{"journal-title":"Design Compiler","year":"0","key":"ref33"},{"article-title":"SIS: A system for sequential circuit synthesis","year":"1992","author":"sentovich","key":"ref32"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657024"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105401"},{"journal-title":"Synthesis and Optimization of Digital Circuits","year":"1994","author":"de micheli","key":"ref37"},{"key":"ref36","first-page":"957","article-title":"Approximate logic synthesis for error tolerant applications","author":"shin","year":"2010","journal-title":"Proc DATE"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333695"},{"key":"ref34","first-page":"825","article-title":"Slack redistribution for graceful degradation under voltage overscaling","author":"kahng","year":"2010","journal-title":"Proc ASP-DAC"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457059"},{"key":"ref40","first-page":"402","article-title":"Perturb and simplify: Optimizing circuits with external don’t cares","author":"chang","year":"1996","journal-title":"Proc ED TC"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2151008"},{"key":"ref12","first-page":"1","article-title":"Sustaining Moore’s law in embedded computing through probabilistic and approximate design: Retrospects and prospects","author":"palem","year":"2009","journal-title":"Proc CASES"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488873"},{"key":"ref14","first-page":"1","article-title":"Best-effort parallel execution framework for recognition and mining applications","author":"meng","year":"2009","journal-title":"Proc IPDPS"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1806596.1806620"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2025113.2025133"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763153"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2008.75"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993675"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763130"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313834"},{"key":"ref27","first-page":"1566","article-title":"A new circuit simplification method for error tolerant applications","author":"shin","year":"2011","journal-title":"Proc DATE"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837492"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837411"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228450"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1594233.1594282"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540710"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024863"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2005.58"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457181"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.917729"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228509"},{"key":"ref22","doi-asserted-by":"crossref","first-page":"1225","DOI":"10.1109\/TVLSI.2009.2020591","article-title":"Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing","volume":"18","author":"zhu","year":"2010","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2007.896937"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2011.51"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429542"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.280"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228504"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/43\/9204502\/8831411-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9204502\/08831411.pdf?arnumber=8831411","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:05:33Z","timestamp":1651068333000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8831411\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,10]]},"references-count":40,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2019.2940680","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2020,10]]}}}