{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:00:08Z","timestamp":1740132008801,"version":"3.37.3"},"reference-count":67,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"U.S. National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1617071","CCF-1718080","CCF-1725657","CCF-1910413"],"award-info":[{"award-number":["CCF-1617071","CCF-1718080","CCF-1725657","CCF-1910413"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2020,10]]},"DOI":"10.1109\/tcad.2019.2940685","type":"journal-article","created":{"date-parts":[[2019,9,11]],"date-time":"2019-09-11T19:54:46Z","timestamp":1568231686000},"page":"2347-2360","source":"Crossref","is-referenced-by-count":4,"title":["Exploiting In-Memory Data Patterns for Performance Improvement on Crossbar Resistive Memory"],"prefix":"10.1109","volume":"39","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4292-3650","authenticated-orcid":false,"given":"Wen","family":"Wen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lei","family":"Zhao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8425-8743","authenticated-orcid":false,"given":"Youtao","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jun","family":"Yang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001139"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001140"},{"key":"ref33","first-page":"31","article-title":"10&#x00D7;10nm&#x00B2; HF\/HfOx crossbar resistive RAM with excellent performance, reliability and low-energy operation","author":"govoreanu","year":"2011","journal-title":"Proc IEEE Int Electron Devices Meeting (IEDM)"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669157"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2015.7357164"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2015.7059070"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898010"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/SISPAD.2014.6931558"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2010.2062187"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2015.2426531"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3287674"},{"key":"ref62","first-page":"88","article-title":"Analog-input analog-weight dot-product operation with Ag\/a-Si\/Pt memristive devices","author":"gao","year":"2012","journal-title":"Proc IEEE\/IFIP 20th Int Conf VLSI Syst Chip (VLSI-SoC)"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/ICRC.2017.8123649"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1109\/NVMSA.2017.8064464"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2014.2310200"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2006.885016"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2017.80"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2011.2165690"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2012.2231683"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131653"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.3390\/electronics7100224"},{"key":"ref2","article-title":"Co-architecting controllers and DRAM to enhance DRAM process scaling","author":"kang","year":"2014","journal-title":"Proc Memory Forum ISCA"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203787"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062191"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3195799"},{"key":"ref21","first-page":"1","article-title":"Wear leveling for crossbar resistive memory","author":"wen","year":"2018","journal-title":"Proc 55th ACM\/ESDA\/IEEE Design Automat Conf (DAC)"},{"key":"ref24","first-page":"282","article-title":"Accelerating write by exploiting PCM asymmetries","author":"yue","year":"2013","journal-title":"Proc IEEE 19th Int Symp High Perform Comput Architect (HPCA)"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/SiPS.2015.7344980"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2016.2645207"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6169027"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2005.1430554"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2017.50"},{"key":"ref59","first-page":"39","article-title":"Thermal-aware optimizations of ReRAM-based neuromorphic computing systems","author":"beigi","year":"2018","journal-title":"Proc 55th Annu Design Autom Conf"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2017.8009177"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062310"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1145\/3291054"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00015"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00039"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.053631140"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173171"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3126532"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2017.110"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.55"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2012.2190369"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056056"},{"key":"ref14","first-page":"58","article-title":"Constructing fast and energy efficient 1TNR based ReRAM crossbar memory","author":"zhao","year":"2017","journal-title":"Proc Int Symp Quality Electronic Design (ISQED)"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001192"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MCE.2016.2614523"},{"key":"ref17","first-page":"756","article-title":"Leader: Accelerating ReRAM-Based Main Memory by Leveraging Access Latency Discrepancy in Crossbar Arrays","author":"hang zhang","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2018.8388846"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2017.8167774"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555760"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555759"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669117"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.24"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557176"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5456923"},{"key":"ref49","article-title":"PARSEC 2.0: A new benchmark suite for chip-multiprocessors","author":"bienia","year":"2009","journal-title":"Proceedings of the 5th Annual Workshop on Modeling Benchmarking and Simulation"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2016.7427985"},{"article-title":"Frequent pattern compression: A significance-based compression scheme for L2 caches","year":"2004","author":"alameldeen","key":"ref46"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2279571"},{"key":"ref48","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1186736.1186737","article-title":"SPEC CPU2006 benchmark descriptions","volume":"34","author":"henning","year":"2006","journal-title":"ACM SIGARCH Comput Architect News"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.1998.655905"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446049"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.65"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2017.34"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/43\/9204502\/8832251-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9204502\/08832251.pdf?arnumber=8832251","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:05:33Z","timestamp":1651068333000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8832251\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,10]]},"references-count":67,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2019.2940685","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2020,10]]}}}