{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,11]],"date-time":"2026-04-11T02:11:33Z","timestamp":1775873493152,"version":"3.50.1"},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61433019"],"award-info":[{"award-number":["61433019"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61872374"],"award-info":[{"award-number":["61872374"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61572508"],"award-info":[{"award-number":["61572508"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2020,10]]},"DOI":"10.1109\/tcad.2019.2944790","type":"journal-article","created":{"date-parts":[[2019,10,4]],"date-time":"2019-10-04T19:54:51Z","timestamp":1570218891000},"page":"2461-2474","source":"Crossref","is-referenced-by-count":19,"title":["HPE: Hierarchical Page Eviction Policy for Unified Memory in GPUs"],"prefix":"10.1109","volume":"39","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8105-8682","authenticated-orcid":false,"given":"Qi","family":"Yu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bruce","family":"Childers","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7878-3998","authenticated-orcid":false,"given":"Libo","family":"Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cheng","family":"Qian","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhiying","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","first-page":"187","article-title":"CAR: Clock with adaptive replacement","author":"bansal","year":"2004","journal-title":"Proc 3rd USENIX Conf File Storage Technol"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/1067627.806596"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.5"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250709"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/511399.511340"},{"key":"ref34","first-page":"115","article-title":"ARC: A self-tuning, low overhead replacement cache","author":"megiddo","year":"2003","journal-title":"Proc 3rd USENIX Conf File Storage Technol"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446077"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123975"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"ref13","article-title":"Parboil: A revised benchmark suite for scientific and commercial throughput computing","author":"stratton","year":"2012"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/InPar.2012.6339595"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815971"},{"key":"ref16","first-page":"323","article-title":"CLOCK-Pro: An effective improvement of the CLOCK replacement","author":"jiang","year":"2005","journal-title":"Proc USENIX Annu Tech Conf"},{"key":"ref17","first-page":"568","article-title":"Supporting $\\times$\n86-64 address translation for 100s of GPU lanes","author":"power","year":"2014","journal-title":"Proc 20th IEEE Int Symp High Perform Comput Architect"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00025"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00036"},{"key":"ref28","year":"2016","journal-title":"NVIDIA Tesla P100"},{"key":"ref4","year":"2011","journal-title":"CUDA C Programming Guide"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1147\/sj.52.0078"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080231"},{"key":"ref6","author":"luitjens","year":"2014","journal-title":"CUDA Streams Best Practices and Common Pitfalls"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2014.6983054"},{"key":"ref5","year":"2011","journal-title":"OpenCL—The Open Standard for Parallel Programming of Heterogeneous Systems"},{"key":"ref8","author":"kyriazis","year":"2012","journal-title":"Heterogeneous System Architecture A Technical Review"},{"key":"ref7","author":"harris","year":"2013","journal-title":"Unified Memory in CUDA 6"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446089"},{"key":"ref9","author":"sakharnykh","year":"2016","journal-title":"Beyond GPU Memory Limits with Unified Memory on Pascal"},{"key":"ref1","year":"2016","journal-title":"GPU Accelerated Applications"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541942"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2731186.2731192"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173169"},{"key":"ref24","author":"sakharnykh","year":"2017","journal-title":"Unified Memory on Pascal and Volta"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056046"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2016.7482091"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919648"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9204502\/08859215.pdf?arnumber=8859215","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:05:08Z","timestamp":1651068308000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8859215\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,10]]},"references-count":35,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2019.2944790","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,10]]}}}