{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,17]],"date-time":"2025-09-17T16:46:00Z","timestamp":1758127560022,"version":"3.37.3"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"NSF of China","doi-asserted-by":"publisher","award":["61672433"],"award-info":[{"award-number":["61672433"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"National Cryptography Fund of China","award":["MMJJ20170210"],"award-info":[{"award-number":["MMJJ20170210"]}]},{"name":"Innovation Fund of Shenzhen Research Committee","award":["201703063000517"],"award-info":[{"award-number":["201703063000517"]}]},{"name":"Shaanxi Provincial Key Research and Development Program","award":["2018KW-005"],"award-info":[{"award-number":["2018KW-005"]}]},{"DOI":"10.13039\/501100010880","name":"Technology Project of State Grid Corporation of China","doi-asserted-by":"publisher","award":["522722180007"],"award-info":[{"award-number":["522722180007"]}],"id":[{"id":"10.13039\/501100010880","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["CNS-1563767","CNS-1527631","CNS-1718586"],"award-info":[{"award-number":["CNS-1563767","CNS-1527631","CNS-1718586"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2020,10]]},"DOI":"10.1109\/tcad.2019.2950380","type":"journal-article","created":{"date-parts":[[2019,10,30]],"date-time":"2019-10-30T20:09:18Z","timestamp":1572466158000},"page":"2124-2137","source":"Crossref","is-referenced-by-count":12,"title":["Memory-Based High-Level Synthesis Optimizations Security Exploration on the Power Side-Channel"],"prefix":"10.1109","volume":"39","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5136-1119","authenticated-orcid":false,"given":"Lu","family":"Zhang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2568-0861","authenticated-orcid":false,"given":"Dejun","family":"Mu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wei","family":"Hu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yu","family":"Tai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jeremy","family":"Blackstone","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9062-5570","authenticated-orcid":false,"given":"Ryan","family":"Kastner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref32","first-page":"218","article-title":"Designing high-quality hardware on a development effort budget: A study of the current state of high-level synthesis","author":"sun","year":"2016","journal-title":"Proc Asia South Pacific Design Autom Conf (ASP-DAC)"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2550501"},{"key":"ref30","first-page":"435","article-title":"System-level optimization of accelerator local memory for heterogeneous systems-on-chip","volume":"36","author":"pilato","year":"2017","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"journal-title":"Vivado design suite user guide-high-level synthesis","year":"2014","key":"ref10"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950423"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2472007"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342189"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2513673"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339221"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645550"},{"key":"ref17","first-page":"13","article-title":"Test vector leakage assessment (TVLA) methodology in practice","volume":"1001","author":"becker","year":"2013","journal-title":"Proc Int Cryptograph Mod Conf"},{"key":"ref18","first-page":"158","article-title":"A testing methodology for side-channel resistance validation","author":"goodwill","year":"2011","journal-title":"NIST Non-invasive Attack Testing Workshop"},{"key":"ref19","first-page":"388","article-title":"Differential power analysis","author":"kocher","year":"1999","journal-title":"Proc Annu Int Cryptol Conf"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2335155"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2014.7032504"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-45234-8_68"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2006.40"},{"key":"ref6","volume":"31","author":"mangard","year":"2007","journal-title":"Power Analysis Attacks Revealing the Secrets of Smart Cards"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2883901"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2857321"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/11545262_12"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ITCC.2004.1286711"},{"key":"ref2","first-page":"918","article-title":"Adaptive Threshold Non-Pareto Elimination: Re-Thinking Machine Learning for System Level Design Space Exploration on FPGAs","author":"pingfan meng","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref9","article-title":"A reversible data hiding method for encrypted images","volume":"6819","author":"puech","year":"2008","journal-title":"Electron Imag"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.83"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-011-0010-2"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268856"},{"key":"ref21","first-page":"172","article-title":"An optimized S-box circuit architecture for low power AES design","author":"morioka","year":"2002","journal-title":"Proc Workshop Cryptographic Hardware Embedded Syst"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-26408-0_8"},{"key":"ref23","first-page":"1","article-title":"Throughput optimization for high-level synthesis using resource constraints","author":"li","year":"2014","journal-title":"Proceedings of the International Workshop on Polyhedral Compilation Techniques (IMPACT'12)"},{"key":"ref26","doi-asserted-by":"crossref","first-page":"163","DOI":"10.7873\/DATE.2015.0798","article-title":"Interplay of loop unrolling and multidimensional memory partitioning in HLS","author":"cilardo","year":"2015","journal-title":"Proc Design Automat Test Europe Conf Exhib"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488748"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/43\/9204502\/8887278-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9204502\/08887278.pdf?arnumber=8887278","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:05:33Z","timestamp":1651068333000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8887278\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,10]]},"references-count":32,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2019.2950380","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2020,10]]}}}