{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,5]],"date-time":"2026-02-05T22:25:49Z","timestamp":1770330349726,"version":"3.49.0"},"reference-count":56,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2020,12,1]],"date-time":"2020-12-01T00:00:00Z","timestamp":1606780800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"name":"National Key Research and Development Program of China","award":["2017YFB1001603"],"award-info":[{"award-number":["2017YFB1001603"]}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61672251"],"award-info":[{"award-number":["61672251"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61732010"],"award-info":[{"award-number":["61732010"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61825202"],"award-info":[{"award-number":["61825202"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61929103"],"award-info":[{"award-number":["61929103"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2020,12]]},"DOI":"10.1109\/tcad.2020.2966482","type":"journal-article","created":{"date-parts":[[2020,1,13]],"date-time":"2020-01-13T15:41:15Z","timestamp":1578930075000},"page":"4669-4682","source":"Crossref","is-referenced-by-count":12,"title":["Miss Penalty Aware Cache Replacement for Hybrid Memory Systems"],"prefix":"10.1109","volume":"39","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3934-7605","authenticated-orcid":false,"given":"Hai","family":"Jin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7873-4838","authenticated-orcid":false,"given":"Di","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4290-1408","authenticated-orcid":false,"given":"Haikun","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6302-813X","authenticated-orcid":false,"given":"Xiaofei","family":"Liao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rentong","family":"Guo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yu","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","year":"2015","journal-title":"Improving Real-Time Performance by Utilizing Cache Allocation Technology"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/2541228.2555307"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2007.4429239"},{"key":"ref32","first-page":"1","article-title":"Toward multi-programmed workloads with different memory footprints: A self-adaptive last level cache scheduling scheme","volume":"61","author":"zhang","year":"2017","journal-title":"Sci China Inf Sci"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1007\/s11432-011-4213-z"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540733"},{"key":"ref37","first-page":"57","article-title":"Vantage: Scalable and efficient fine-grain cache partitioning","author":"sanchez","year":"2011","journal-title":"2011 38th Annual International Symposium on Computer Architecture (ISCA) ISCA"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.24"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2014.6974670"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/MSST.2007.4367989"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815971"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250709"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835921"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2016.7495289"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2013.6582088"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2987550.2987570"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.98"},{"key":"ref24","first-page":"1","article-title":"ShiftsReduce: Minimizing shifts in racetrack memory 4.0","volume":"abs 1903 3597","author":"khan","year":"2019","journal-title":"CoRR"},{"key":"ref23","first-page":"756","article-title":"Leader: Accelerating ReRAM-Based Main Memory by Leveraging Access Latency Discrepancy in Crossbar Arrays","author":"hang zhang","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref26","author":"hady","year":"2019","journal-title":"Intel Optane Technology Delivers New Levels of Endurance"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1557\/mrs.2019.205"},{"key":"ref50","first-page":"1","article-title":"Design of CPU cache memories","author":"smith","year":"1987","journal-title":"Proc IEEE TENCON"},{"key":"ref51","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2024716.2024718","article-title":"The Gem5 simulator","volume":"39","author":"binkert","year":"2011","journal-title":"SIGARCH Comput Archit News"},{"key":"ref56","first-page":"1","article-title":"CACTI 5.1","author":"thoziyoor","year":"2008"},{"key":"ref55","first-page":"1","article-title":"Architecting for power management: The IBM POWER7 approach","author":"ware","year":"2010","journal-title":"Proc IEEE Int Symp High Perform Comput Archit (HPCA)"},{"key":"ref54","first-page":"5","article-title":"Consistent and durable data structures for non-volatile byte-addressable memory","author":"venkataraman","year":"2011","journal-title":"Proc 9th USENIX Conf File Storage Technol"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950379"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2012.82"},{"key":"ref10","first-page":"45","article-title":"Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design","author":"chen","year":"2012","journal-title":"Proc Design and Test in Europe (DATE) Conf"},{"key":"ref11","year":"2019","journal-title":"2016 Analyst Conference"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.47"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2014.18"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.10"},{"key":"ref14","first-page":"936","article-title":"An Operating System Level Data Migration Scheme in Hybrid DRAM-NVM Memory Architecture","author":"reza salkhordeh","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835944"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835933"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228439"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2818950.2818974"},{"key":"ref19","first-page":"1","article-title":"Basic performance measurements of the Intel Optane DC persistent memory module","volume":"abs 1903 5714","author":"izraelevitz","year":"2019","journal-title":"CoRR"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540744"},{"key":"ref3","first-page":"234","article-title":"i&#x00B2;WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations","author":"wang","year":"2013","journal-title":"Proc IEEE Int Symp High Perform Comput Archit (HPCA)"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669164"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485961"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630086"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2014.6974658"},{"key":"ref49","year":"2019","journal-title":"Cache replacement policies"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1995896.1995911"},{"key":"ref46","author":"paper","year":"2002","journal-title":"Inside the Intel Itanium 2 Processor"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1587\/transcom.2017EBP3299"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2004.1297303"},{"key":"ref47","first-page":"218","author":"tanenbaum","year":"2001","journal-title":"Modern Operating Systems"},{"key":"ref42","year":"2019","journal-title":"Power Management of the Third Generation Intel Core Micro Architecture Formerly Codenamed IVY Bridge"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TII.2016.2645941"},{"key":"ref44","year":"2019","journal-title":"Nvm technologies"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9265421\/08957668.pdf?arnumber=8957668","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:49:21Z","timestamp":1641988161000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8957668\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,12]]},"references-count":56,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2020.2966482","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,12]]}}}