{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,11]],"date-time":"2025-09-11T07:06:51Z","timestamp":1757574411434,"version":"3.37.3"},"reference-count":60,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2020,12,1]],"date-time":"2020-12-01T00:00:00Z","timestamp":1606780800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,12,1]],"date-time":"2020-12-01T00:00:00Z","timestamp":1606780800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,12,1]],"date-time":"2020-12-01T00:00:00Z","timestamp":1606780800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"French-Slovak Bilateral Collaborative Program PHC-STEFANIK"},{"DOI":"10.13039\/501100005357","name":"Slovak Research and Development Agency","doi-asserted-by":"publisher","award":["SK-FR-2017-0003"],"award-info":[{"award-number":["SK-FR-2017-0003"]}],"id":[{"id":"10.13039\/501100005357","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100006109","name":"Scientific Grant Agency of the Ministry of Education, Science, Research and Sport of the Slovak Republic and the Slovak Academy of Sciences","doi-asserted-by":"publisher","award":["VEGA 1\/0354\/17"],"award-info":[{"award-number":["VEGA 1\/0354\/17"]}],"id":[{"id":"10.13039\/501100006109","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2020,12]]},"DOI":"10.1109\/tcad.2020.2966676","type":"journal-article","created":{"date-parts":[[2020,1,14]],"date-time":"2020-01-14T21:13:06Z","timestamp":1579036386000},"page":"4854-4866","source":"Crossref","is-referenced-by-count":13,"title":["Development of Programmable Logic Array for Multiple-Valued Logic Functions"],"prefix":"10.1109","volume":"39","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1932-3603","authenticated-orcid":false,"given":"Vitaly","family":"Levashenko","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Igor","family":"Lukyanchuk","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9087-0311","authenticated-orcid":false,"given":"Elena","family":"Zaitseva","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6450-5417","authenticated-orcid":false,"given":"Miroslav","family":"Kvassay","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2835-9114","authenticated-orcid":false,"given":"Jan","family":"Rabcan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9683-5376","authenticated-orcid":false,"given":"Patrik","family":"Rusnak","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref39","DOI":"10.1103\/PhysRevB.90.024102"},{"doi-asserted-by":"publisher","key":"ref38","DOI":"10.1080\/10584580802107684"},{"year":"2011","author":"nielsen","journal-title":"Quantum Computation and Quantum Information 10th Anniversary Edition","key":"ref33"},{"key":"ref32","first-page":"17","article-title":"Review of quaternary adders in voltage mode multi-valued logic","volume":"2013","author":"umredkar","year":"2013","journal-title":"Int J Comput Appl"},{"doi-asserted-by":"publisher","key":"ref31","DOI":"10.1109\/ISMVL.2018.00016"},{"doi-asserted-by":"publisher","key":"ref30","DOI":"10.1109\/TNANO.2004.842068"},{"doi-asserted-by":"publisher","key":"ref37","DOI":"10.1021\/nl503070f"},{"doi-asserted-by":"publisher","key":"ref36","DOI":"10.1038\/srep42196"},{"key":"ref35","article-title":"The device physics of cellular logic gates","author":"weiss","year":"2002","journal-title":"Proc 1st Workshop Non Silicon Comput"},{"doi-asserted-by":"publisher","key":"ref34","DOI":"10.1007\/s11128-015-1011-3"},{"doi-asserted-by":"publisher","key":"ref60","DOI":"10.1103\/RevModPhys.84.119"},{"doi-asserted-by":"publisher","key":"ref28","DOI":"10.1109\/ISMVL.2000.848636"},{"doi-asserted-by":"publisher","key":"ref27","DOI":"10.1109\/55.491836"},{"doi-asserted-by":"publisher","key":"ref29","DOI":"10.1109\/JPROC.2007.911051"},{"key":"ref2","first-page":"141","article-title":"Towards nanocomputer architecture","volume":"6","author":"beckett","year":"2002","journal-title":"Proc 7th Asia–Pac Comput Syst Archit Conf (ACSAC)"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/TC.1984.1676392"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1109\/TCT.1955.6500156"},{"key":"ref22","first-page":"3","author":"brusentzov","year":"1962","journal-title":"The SETUN small automatic digital computer"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1109\/PGEC.1963.263596"},{"doi-asserted-by":"publisher","key":"ref24","DOI":"10.1109\/JSSC.1985.1052354"},{"doi-asserted-by":"publisher","key":"ref23","DOI":"10.1023\/B:ALOG.0000024066.66847.89"},{"doi-asserted-by":"publisher","key":"ref26","DOI":"10.1109\/JSSC.1986.1052493"},{"doi-asserted-by":"publisher","key":"ref25","DOI":"10.1109\/TC.1986.1676727"},{"key":"ref50","doi-asserted-by":"crossref","first-page":"69","DOI":"10.1049\/ip-e.1993.0009","article-title":"canonical restricted mixed-polarity exclusive-or sums of products and the efficient algorithm for their minimisation","volume":"140","author":"csanky","year":"1993","journal-title":"Computers and Digital Techniques IEE Proceedings-"},{"doi-asserted-by":"publisher","key":"ref51","DOI":"10.1109\/12.600830"},{"doi-asserted-by":"publisher","key":"ref59","DOI":"10.1038\/ncomms9542"},{"doi-asserted-by":"publisher","key":"ref58","DOI":"10.1109\/MSPCT.2017.8363975"},{"doi-asserted-by":"publisher","key":"ref57","DOI":"10.1109\/EURMIC.1999.794494"},{"key":"ref56","first-page":"47","article-title":"Switching activity minimization in combinational logic design","author":"menon","year":"2004","journal-title":"Proc Int Conf Embedded Syst Appl (ESA)"},{"year":"1997","author":"knuth","journal-title":"The art of computer programming volume 1 (3rd ed ) Fundamental algorithms","key":"ref55"},{"year":"2003","author":"balch","journal-title":"Complete Digital Design A Comprehensive Guide to Digital Electronics and Computer System Architecture","key":"ref54"},{"doi-asserted-by":"publisher","key":"ref53","DOI":"10.1016\/j.compstruc.2006.10.010"},{"doi-asserted-by":"publisher","key":"ref52","DOI":"10.1109\/TC.2011.124"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.2307\/2370324"},{"key":"ref11","first-page":"87","article-title":"On three-valued logic","author":"?ukasiewicz","year":"1970","journal-title":"Jan ?ukasiewicz Selected Works"},{"year":"1993","author":"epstein","journal-title":"Multiple-Valued Logic Design An Introduction","key":"ref40"},{"key":"ref12","first-page":"207","article-title":"Modular representation of finite algebras","volume":"1","author":"bernstein","year":"1928","journal-title":"Proc 7th Int Congr Math"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/TEC.1958.5222096"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1080\/00207218908921127"},{"year":"1990","author":"kukharev","journal-title":"Multiple-Valued Data Processing Algorithms and Systolic Processors","key":"ref15"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1073\/pnas.21.5.252"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1109\/MC.1974.6323304"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1007\/978-3-319-90936-3"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1007\/BF01038476"},{"key":"ref4","first-page":"256","article-title":"Multi-valued logic circuit design and implementation","volume":"3","author":"choi","year":"2015","journal-title":"Int J Electron Elect Eng"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/ISMVL.2018.00041"},{"year":"1958","author":"boole","journal-title":"An investigation of the Laws of Thought","key":"ref6"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/ISMVL.2018.00043"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1007\/978-3-319-67295-3"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1002\/j.1538-7305.1949.tb03624.x"},{"year":"1970","author":"bellman","journal-title":"Introduction to Matrix Analysis","key":"ref49"},{"key":"ref9","volume":"2","author":"yanushkevich","year":"2005","journal-title":"Decision Diagram Techniques for Micro- and Nanoelectronic Design Handbook"},{"doi-asserted-by":"publisher","key":"ref46","DOI":"10.1109\/12.21150"},{"doi-asserted-by":"publisher","key":"ref45","DOI":"10.1007\/s11390-005-0895-2"},{"doi-asserted-by":"publisher","key":"ref48","DOI":"10.1080\/00207219308907144"},{"doi-asserted-by":"publisher","key":"ref47","DOI":"10.2200\/S00420ED1V01Y201205DCS037"},{"doi-asserted-by":"publisher","key":"ref42","DOI":"10.1109\/ISMVL.2004.1319915"},{"doi-asserted-by":"publisher","key":"ref41","DOI":"10.1007\/BF02948902"},{"doi-asserted-by":"publisher","key":"ref44","DOI":"10.1109\/TCAD.2015.2488484"},{"doi-asserted-by":"publisher","key":"ref43","DOI":"10.1109\/MWSCAS.1993.343412"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9265421\/08959323.pdf?arnumber=8959323","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:06:26Z","timestamp":1651068386000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8959323\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,12]]},"references-count":60,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2020.2966676","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2020,12]]}}}