{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,27]],"date-time":"2026-05-27T10:42:08Z","timestamp":1779878528130,"version":"3.53.1"},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000181","name":"Air Force Office of Scientific Research, National Defense Science and Engineering Graduate Fellowship, 32 CFR 168a, Drexel Ventures Innovation Fund","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000181","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100006602","name":"Air Force Research Laboratory","doi-asserted-by":"publisher","award":["FA8075-14-D0025\/DSTAT-15-1196"],"award-info":[{"award-number":["FA8075-14-D0025\/DSTAT-15-1196"]}],"id":[{"id":"10.13039\/100006602","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CNS-1751032"],"award-info":[{"award-number":["CNS-1751032"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2021,1]]},"DOI":"10.1109\/tcad.2020.2994259","type":"journal-article","created":{"date-parts":[[2020,5,12]],"date-time":"2020-05-12T23:03:15Z","timestamp":1589324595000},"page":"11-23","source":"Crossref","is-referenced-by-count":15,"title":["Synthesis of Hidden State Transitions for Sequential Logic Locking"],"prefix":"10.1109","volume":"40","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6588-4167","authenticated-orcid":false,"given":"Kyle","family":"Juretus","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4230-1795","authenticated-orcid":false,"given":"Ioannis","family":"Savidis","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2010.5537093"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2016.7538898"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/2902961.2902972"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715053"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/800157.805047"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1137\/0201010"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2017.7951805"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3060403.3060469"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2017.2740364"},{"key":"ref13","first-page":"936","article-title":"Functional analysis attacks on logic locking","author":"sirone","year":"2019","journal-title":"Proc IEEE Design Autom Test Eur Conf Exhibit"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8714924"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.193"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.24"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2028166"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2017.8050606"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2016.7428086"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2925387"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403631"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2007.4397343"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.7"},{"key":"ref6","first-page":"127","article-title":"Mitigating SAT attack on logic locking","author":"xie","year":"2016","journal-title":"Proc Int Conf Cryptograph Hardw Embedded Syst"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203757"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2015.7140252"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3133956.3133985"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2016.7495588"},{"key":"ref2","year":"2012","journal-title":"Trends in the Global IC Design Service Market"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2750088"},{"key":"ref1","year":"2011","journal-title":"Trusted integrated chips (TIC) program"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2012.2188769"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2004.48"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2007.186"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351412"},{"key":"ref23","first-page":"1","article-title":"Active hardware metering for intellectual property protection and security","author":"alkabani","year":"2007","journal-title":"Proc 16th USENIX Security Symp"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2697960"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2459976.2459985"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/43\/9312500\/9091551-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9312500\/09091551.pdf?arnumber=9091551","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:49:28Z","timestamp":1652194168000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9091551\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,1]]},"references-count":35,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2020.2994259","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,1]]}}}