{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:00:27Z","timestamp":1740132027078,"version":"3.37.3"},"reference-count":39,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2020,11,1]],"date-time":"2020-11-01T00:00:00Z","timestamp":1604188800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,11,1]],"date-time":"2020-11-01T00:00:00Z","timestamp":1604188800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,11,1]],"date-time":"2020-11-01T00:00:00Z","timestamp":1604188800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"Department of Energy through the Early Career Award, National Science Foundation","doi-asserted-by":"publisher","award":["NSF-1801599"],"award-info":[{"award-number":["NSF-1801599"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["2018-TS-2860"],"award-info":[{"award-number":["2018-TS-2860"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation Graduate Research Fellowship Program","doi-asserted-by":"publisher","award":["1144246","DGE-1842473"],"award-info":[{"award-number":["1144246","DGE-1842473"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2020,11]]},"DOI":"10.1109\/tcad.2020.3013075","type":"journal-article","created":{"date-parts":[[2020,10,2]],"date-time":"2020-10-02T20:24:18Z","timestamp":1601670258000},"page":"4078-4089","source":"Crossref","is-referenced-by-count":2,"title":["SaeCAS: Secure Authenticated Execution Using CAM-Based Vector Storage"],"prefix":"10.1109","volume":"39","author":[{"given":"Orlando","family":"Arias","sequence":"first","affiliation":[]},{"given":"Dean","family":"Sullivan","sequence":"additional","affiliation":[]},{"given":"Haoqi","family":"Shan","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8791-0597","authenticated-orcid":false,"given":"Yier","family":"Jin","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","first-page":"161","article-title":"Control-flow bending: On the effectiveness of control-flow integrity","author":"carlini","year":"2015","journal-title":"Proc 24th USENIX Secur Symp (USENIX Security)"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351461"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-34961-4_14"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/1064978.1065034"},{"journal-title":"Leon 3 synthesizable processor","year":"2020","author":"research","key":"ref31"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1007\/s11432-015-5459-7"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2518219"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2316733"},{"key":"ref35","first-page":"265","article-title":"Integral cryptanalysis of round-reduced prince cipher","volume":"16","author":"posteuca","year":"2015","journal-title":"Proc Romanian Acad A"},{"key":"ref34","first-page":"92","article-title":"Security analysis of prince","author":"jean","year":"2013","journal-title":"Fast Software Encryption Third International Workshop Proceedings"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3321705.3329815"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/EuroSP.2018.00023"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/948109.948146"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/948109.948147"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1920261.1920268"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2508859.2516670"},{"journal-title":"LPC55S6x 32-b Arm Cortex-M33 Microcontroller Rev 1 9","year":"2020","key":"ref16"},{"journal-title":"LPC55S69 Security Solutions for IoT","year":"2019","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/j.cose.2017.03.013"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/359168.359176"},{"article-title":"LLVM: An infrastructure for multi-stage optimization","year":"2002","author":"lattner","key":"ref28"},{"key":"ref4","first-page":"1","article-title":"Smart: Secure and minimal architecture for (establishing dynamic) root of trust","volume":"12","author":"eldefrawy","year":"2012","journal-title":"Proc NDSS"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/3129743.3129751"},{"journal-title":"LO-FAT Low-Overhead Control Flow ATtestation in Hardware","year":"2017","author":"dessouky","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203803"},{"journal-title":"BEEBS Open Benchmarks for Energy Measurements on Embedded Platforms","year":"2013","author":"pallister","key":"ref29"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2939918.2939938"},{"key":"ref8","first-page":"473","article-title":"LAHEL: Lightweight attestation hardening embedded devices using macrocells","author":"arias","year":"2020","journal-title":"Proc IEEE Symp Hardware-Oriented Security Trust (HOST)"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240821"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2976749.2978358"},{"journal-title":"Execution integrity with in-place encryption","year":"2017","author":"sullivan","key":"ref9"},{"journal-title":"Hack Causes Pacemakers to Deliver Life-Threatening Shocks","year":"2018","author":"goodwin","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218514"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/AsianHOST47458.2019.9006705"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC47756.2020.9045426"},{"journal-title":"Avalon Interface Specifications","year":"2020","key":"ref24"},{"journal-title":"ORCA FPGA-Optimized RISC-V","year":"2016","key":"ref23"},{"journal-title":"WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores","year":"2010","key":"ref26"},{"journal-title":"AMBA AXI and ACE Protocol Specification Documentation","year":"2019","key":"ref25"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9244237\/09211555.pdf?arnumber=9211555","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:04:54Z","timestamp":1651068294000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9211555\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,11]]},"references-count":39,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2020.3013075","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2020,11]]}}}