{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,7]],"date-time":"2026-04-07T21:51:46Z","timestamp":1775598706952,"version":"3.50.1"},"reference-count":34,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T00:00:00Z","timestamp":1619827200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T00:00:00Z","timestamp":1619827200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T00:00:00Z","timestamp":1619827200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Beijing Municipal Science and Technology Program","award":["Z201100004220007"],"award-info":[{"award-number":["Z201100004220007"]}]},{"name":"Area Research and Development Program of Guangdong Province","award":["2018B030338001"],"award-info":[{"award-number":["2018B030338001"]}]},{"name":"Beijing Academy of Artificial Intelligence"},{"name":"Alibaba Innovative Research Program"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2021,5]]},"DOI":"10.1109\/tcad.2020.3015465","type":"journal-article","created":{"date-parts":[[2020,8,10]],"date-time":"2020-08-10T21:37:20Z","timestamp":1597095440000},"page":"864-877","source":"Crossref","is-referenced-by-count":10,"title":["STAR: Synthesis of Stateful Logic in RRAM Targeting High Area Utilization"],"prefix":"10.1109","volume":"40","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1630-9550","authenticated-orcid":false,"given":"Feng","family":"Wang","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4932-3655","authenticated-orcid":false,"given":"Guojie","family":"Luo","sequence":"additional","affiliation":[]},{"given":"Guangyu","family":"Sun","sequence":"additional","affiliation":[]},{"given":"Jiaxi","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Jinfeng","family":"Kang","sequence":"additional","affiliation":[]},{"given":"Yuhao","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Dimin","family":"Niu","sequence":"additional","affiliation":[]},{"given":"Hongzhong","family":"Zheng","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","first-page":"1423","article-title":"XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks","author":"sun","year":"2018","journal-title":"Proc Design Autom Test Eur (DATE)"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.55"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001139"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001140"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744783"},{"key":"ref10","first-page":"677","article-title":"A neutral netlist of 10 combinational benchmark circuits and a target translator in fortran","author":"brglez","year":"1985","journal-title":"Proc Int Symp Circuits Syst (ISCAS)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2763171"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2018.10.001"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3287672"},{"key":"ref14","first-page":"372","article-title":"SAID: A supergate-aided logic synthesis flow for memristive crossbars","author":"tenace","year":"2019","journal-title":"Proc Design Autom Test Eur (DATE)"},{"key":"ref15","article-title":"SIMPLER MAGIC: Synthesis and mapping of in-memory logic executed in a single row to improve throughput","author":"ben-hur","year":"2019","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref16","author":"yang","year":"1991","journal-title":"Logic Synthesis and Optimization Benchmarks User Guide Version 3 0"},{"key":"ref17","first-page":"225","article-title":"Simple magic: Synthesis and in-memory mapping of logic execution for memristor-aided loGIC","author":"hur","year":"2017","journal-title":"Proc Int Conf Comput -Aided Design (ICCAD)"},{"key":"ref18","first-page":"1","article-title":"Iwls’93 benchmark set: Version 4.0","author":"mcelvain","year":"1993","journal-title":"Proc Distrib MCNC Int Workshop Logic Synthesis Benchmark Distrib"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2846699"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351561"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"873","DOI":"10.1038\/nature08940","article-title":"‘Memristive’ switches enable ‘stateful’logic operations via material implication","volume":"464","author":"borghetti","year":"2010","journal-title":"Nature"},{"key":"ref27","first-page":"1628","article-title":"Practical challenges in delivering the promises of real processing-in-memory machines","author":"talati","year":"2018","journal-title":"Proc Design Autom Test Eur (DATE)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2280296"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1002\/adma.201602418"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2018.8465706"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2357292"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2019.000-8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240811"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2010.2070830"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2016.2570248"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/359576.359579"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898064"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ICSICT.2018.8565029"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746281"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056056"},{"key":"ref23","year":"2007","journal-title":"ABC A System for Sequential Synthesis and Verification Release 70930"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062337"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1016\/0096-0551(81)90048-5"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9409805\/09163321.pdf?arnumber=9163321","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:49:29Z","timestamp":1652194169000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9163321\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,5]]},"references-count":34,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2020.3015465","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,5]]}}}